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SEGA Confidential
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SEGA Confidential


TM
1994 SEGA. All Rights Reserved.
VDP2
User's Manual
Version 1.1
Doc. #ST-58-R2-060194
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SEGA Confidential


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VDP2 User's Manual
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SEGA Confidential

REFERENCES
In translating/creating this document, certain technical words and/or phrases were interpreted
with the assistance of the technical literature listed below.
1.
KenKyusha New Japanese-English Dictionary
1974 Edition
2.
Nelson's Japanese-English Character Dictionary
2nd revised version
3.
Microsoft Computer Dictionary
4.
Japanese-English Computer Terms Dictionary
Nichigai Associates
4th version
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SEGA Confidential


Preface
This manual describes the VDP2 (Video Display Processor 2) and how to use it. The VDP2
controls the scroll screen control and the display priority control.
Manual Notations
Notations within this manual are described below.
Binary, hexadecimal
Binary notation has a B attached at the end (as in 100B); however, B may be omitted when
binary notation is obvious. Hexadecimal notation has an H attached at the end (as in 00H
and FFH).
Units
1 Kbyte is 1024 bytes. 1 Mbit is 1024 Kbits, or 1,048,576 bits.
MSB, LSB
The structure of byte and word shows the MSB (most significant bit) on the left and LSB (least
significant bit) on the right.
An undefined bit
A bit not defined by the register is shown as a dash. A "0" should be written into an undefined
bit of the register. Bits not defined by data of tables defined by VRAM are shown as shaded.
As a rule, a 0 should be written, providing that the undefined bit is ignored.
Byte, word, bit
Bits, as in digits of 0 and 1, are the lowest unit of data. A byte consists of 8 bits. A word consists
of 2 bytes, and begins from an even address.
Boundary
A boundary defines data from an address divisible by a selected value. For example, data for a
20H-byte boundary is defined at addresses beginning from 20H, 40H, and so on. A word is a
2-byte boundary.
Address
All addresses defined by VDP2 are relative addresses within VDP2. The first address of VDP2
begins from 5E00000H. For example, VRAM is at 000000H address of the relative address, and
begins from 5E00000H address of the absolute address. The TV screen mode register is at
180000H address of the relative address, and is set at address 5F80000H of the absolute address.
i
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Manual Structure
The main items described in each chapter are as follows.
Table 1.
Chapters and Main Items
ii
Chapter Name
Contents
Chapter 1 VDP2 Functions
VDP2 Functions
Chapter 2 TV Screen
TV Screen Mode, Normal, Hi-Res, Exclusive
Monitor, Interlace Mode, External Signal, H
-
Counter, V-Counter, Exclusive Hi-Res Setting
Chapter 3 RAM
VRAM Size, Address Map, VRAM, Color RAM,
Register, VRAM Change, VRAM Bank
Partition, VRAM Access Method, Color RAM
Mode
Chapter 4 Scroll Screen
Cell, Character Color Count, Transparent Dot,
Character Pattern, Pattern Name Table,
Special Function Bit, Reverse Function Bit,
Page, Plane, Map, Bitmap, Screen-Over
Process, Mosaic Process
Chapter 5 Normal Scroll Screen
Screen Scroll, Scaling, Line Scroll, Vertical Cell
Scroll Coordinates
Chapter 6 Rotation Scroll Screen
Rotation Scroll Increment, Rotation Scroll
Screen Display, Rotation Parameter
Coefficient Table
Chapter 7 Line Screen
Line Color Screen, Back Screen
Chapter 8 Window
Normal Rectangular Window, Normal Line
Window, Sprite Window
Chapter 9 Sprite Data
Sprite Type, Sprite Color Mode, Priority, Color
Calculation
Chapter 10 Dot Color Data
Palette Format, RGB Format, Sprite Dot, Scroll
Dot, Special Function Code
Chapter 11 Priority Function
Priority Number, Line Color Screen Insertion
Chapter 12 Color Calculation
Color Calculation, Extended Color Calculation,
Special Color Calculation, Gradation
Calculation
Chapter 13 Color Offset Function
Color Offset
Chapter 14 Shadow Function
Normal Shadow, MSB Shadow
Chapter 15 How To Use VDP2
Operation Flow Chart, How to use RAM, Bit
Structure
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Function
Details
Chapter
Overview
~
1
VDP2 Functions
TV Screen Configuration, Designate Display
Area, Boarder Area
2.1
TV Screen Configuration
TV Screen
TV Screen Mode, Normal, Hi-Res, Exclusive
Monitor
2.2
TV Screen Mode
Interlace, Non-interlace, Single-Density Interlace,
Double-Density Interlace
2.3
Interlace Mode
Address Map
3.1
Address Map
Size
3.1
Address Map
RAM
VRAM
Change
3.2
VRAM Change
Bank Partition
3.3
VRAM Bank Partition
Access During Display
3.4
How to Access VRAM
During Display
Color RAM Mode
3.5
Color RAM Mode
Screen Display
4.1
Screen Display Control
Character
Color Count
Bitmap Color
Count
4.3
Cell
Color
Palette Format
Dot Color Data
10.1
Palette Format Dot Color
Data
Normal Scroll
Screen
RGB Format
Dot Color Data
10.2
RGB Format Dot Color Data
Scroll Screen
Rotation Scroll
Screen
Color RAM
Mode
3.5
Color RAM Mode
Cell
4.3
Cell
Character
Pattern
4.4
Character Pattern
Cell Format
Pattern Name
Table (Page)
4.6
Pattern Name Table (Page)
Plane
4.7
Plane
Map
4.8
Map
Bitmap Format
4.9
Bitmap
Display Area, Screen-Over
4.10
Display Area
Mosaic Process
4.11
Mosaic Process
Screen Scroll Function
5.1
Screen Scroll Function
Scale Function
5.2
Scale Function
Line Scroll Function, Vertical
Cell Scroll Function
5.3
Line & Vertical Cell Scroll
Function
iv
Table 2.
Functions, their chapters and sections
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v
Function
Details
Chapter
Coordinates Calculation
6.1
Rotation Scroll Coordinates
Calculation
Rotation
Display Control
6.2
Rotation Scroll Screen
Display Control
Scroll Screen
Rotation Parameter Control
6.3
8
Rotation Parameter Control
Window
Scroll Screen
Coefficient Control
6.4
Coefficient Table Control
Line Screen
Line Color Screen
7.1
6.4
11.3
Line Color Screen
Coefficient Table Control
Line Color Screen Insertion
Back Screen
7.2
Back Screen
Window
Normal Rectangular Window, Normal Line
Window, Sprite Window, Window Effective Area
8
9.1
Window
Sprite Data
Sprite Data, Type, Color Mode
9.1
Sprite Data
Priority and Color Calculation
9.2
Priority and Color
Calculation
Sprite
Sprite Window
8
9.1
Window
Sprite Data
Dot Color
Palette Format
10.1
Palette Format Dot Color
Data
Data
RGB Format
10.2
RGB Format Dot Color Data
Color RAM Mode
3.5
Color RAM Mode
Priority Function
11.1
9.2
Priority Function
Priority and Color
Calculation
Priority
Special Priority Function
11.2
10.3
Special Priority Function
Special Function Code
Line Color Screen Insertion
11.3
7.1
Line Color Screen Insertion
Line Color Screen
Color Calculation Function,
Extended Color Calculation
Function
12.1
7.1
Color Calculation Function
Line Color Screen
Image Process
Color
Special Color Calculation
Function
12.3
10.3
Special Color Calculation
Function
Special Function Code
Gradation Calculation Function 12.2
Gradation Calculation
Function
Color Calculation Window
8
Window
Color Offset Function
13
Color Offset Function
Shadow
Normal Shadow, MSB Shadow 14
9.1
Shadow Function
Sprite Data
Table 2.
Functions, their chapters and sections (continued)
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vi
Table of Contents
Preface ............................................................................................................................ i
Manual Notation .................................................................................................. i
Manual Structure ............................................................................................... iii
List of Figures................................................................................................................ xi
List of Tables ............................................................................................................... xiv
Chapter 1 VDP2 Functions ........................................................................................... 1
Introduction......................................................................................................... 2
1.1 System Configuration ................................................................................... 2
1.2 Address Map ................................................................................................ 3
VRAM ..................................................................................................... 3
Color RAM .............................................................................................. 3
Register .................................................................................................. 4
1.3 Scroll Function.............................................................................................. 5
Display Screen ....................................................................................... 5
Scroll Screen .......................................................................................... 6
Line Screen ............................................................................................ 7
Windows ................................................................................................. 7
1.4 Priority Function ........................................................................................... 8
Priority Function ...................................................................................... 8
Color Calculation Function ..................................................................... 8
Color Offset Function .............................................................................. 8
Shadow Function .................................................................................... 9
Chapter 2 TV Screen .................................................................................................. 11
2.1 TV Screen Mode ........................................................................................12
Special High Resolution Graphic Mode ................................................ 13
2.2 Interlace Mode............................................................................................ 14
2.3 TV Screen Structure ................................................................................... 15
2.4 TV Screen Mode Register .......................................................................... 16
2.5 External Signals and Scan Conditions ....................................................... 19
External Signal Enable Register ........................................................... 19
Screen Status Register ........................................................................ 21
H Counter Register ............................................................................... 23
V Counter Register ............................................................................... 24
Chapter 3 RAM ...........................................................................................................25
Introduction....................................................................................................... 26
3.1 Address Map .............................................................................................. 26
VRAM Size Register ............................................................................. 28
3.2 VRAM Bank Partitioning ............................................................................. 29
RAM Control Register .......................................................................... 29
3.3 Accessing VRAM During Display Interval .................................................. 31
VRAM Access During Display Interval ................................................. 31
I
mage Data Access ..............................................................................32
Vertical Cell Scroll Table Data Access .................................................. 35
Read/Write Access by the CPU ............................................................ 35
VRAM Cycle Pattern Selection Process ............................................... 37
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VRAM Cycle Pattern Register .............................................................. 39
3.4 Color RAM Mode ........................................................................................ 43
RAM Control Register .......................................................................... 45
Chapter 4 Scroll Screen .............................................................................................. 47
4.1 Screen Display Control .............................................................................. 48
Screen Display Enable Register ........................................................... 48
4.2 Scroll Screen Structure .............................................................................. 50
Cell Format ....................................................................................................... 50
Bit Map Format ................................................................................................. 52
4.3 Cell ............................................................................................................. 53
Character Color Number ...................................................................... 53
Cell Data Configuration ........................................................................ 53
Transparent Dots .................................................................................. 57
RGB Format Dot Data .......................................................................... 58
4.4 Character Patterns ..................................................................................... 59
Character Size and Cell Arrangement .................................................. 59
4.5 Character Control Register ........................................................................ 60
4.6 Pattern Name Table (Page) ........................................................................ 64
Pattern Name Table Data Configuration ............................................... 64
Pattern Name Data ............................................................................... 69
Character Number ................................................................................ 74
Palette Number ..................................................................................... 74
Special Function Bit .............................................................................. 74
Reverse (Flip) Function Bit ................................................................... 75
Pattern Name Control Register ............................................................ 76
4.7 Planes ........................................................................................................ 79
Plane Size ............................................................................................ 79
Plane Size Register .............................................................................. 80
4.8 Maps ........................................................................................................... 82
Map Selection Register ........................................................................ 82
Map Size ............................................................................................... 84
Map Offset Register .............................................................................. 85
Normal Scroll Screen Map Register ..................................................... 87
Rotation Scroll Surface Map Register .................................................. 89
4.9 Bit Maps ..................................................................................................... 93
Bit Map Size ......................................................................................... 93
Bit Map Color Number .......................................................................... 93
Bit Map Pattern ..................................................................................... 95
Bit Map Palatte Number ..................................................................... 111
Special Function Bit ............................................................................ 111
Bit Map Palatte Number Register ....................................................... 112
4.10 Display Area ........................................................................................... 114
Display Area ....................................................................................... 114
Screen-Over Process ......................................................................... 115
Display-Over Pattern Name ............................................................... 115
Screen-Over Pattern Name Register ................................................. 116
4.11 Mosaic Process ...................................................................................... 117
Mosaic Control Register ..................................................................... 118
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Chapter 5 Normal Scroll Screen ............................................................................... 121
Introduction..................................................................................................... 122
5.1 Screen Scroll Function ............................................................................. 122
Screen Scroll Value Register .............................................................. 123
5.2 Expansion/Contraction Function .............................................................. 126
Coordinate Increment Register .......................................................... 127
Reduction Enable Register ................................................................. 129
5.3 Line and Vertical Cell Scroll Function ....................................................... 131
Line Scroll Function ............................................................................ 131
Vertical Cell Scroll Function ................................................................ 134
Line and Vertical Cell Scroll Control Register ..................................... 137
Line Scroll Table Address Register ..................................................... 140
Vertical Cell Scroll Table Address Register ........................................ 141
Chapter 6 Rotation Scroll Screen ............................................................................. 143
Introduction..................................................................................................... 144
6.1 Rotation Scroll Coordinate Operation ...................................................... 144
6.2 Rotation Scroll Screen Display Control .................................................... 148
RAM Control Register ........................................................................ 148
6.3 Rotation Parameter Control ..................................................................... 151
Data Configuration of the Rotation Parameter Table .......................... 153
Rotation Parameter Table ................................................................... 155
Rotation Parameter Read Control Register ........................................ 157
Rotation Parameter Table Address Register ...................................... 158
Rotation Read Out of the Frame Buffer .............................................. 159
Rotation Parameter Change ............................................................... 160
Rotation Parameter Mode Register .................................................... 162
6.4 Coefficient Table Control .......................................................................... 163
Line Color Screen Data ...................................................................... 164
Bit Configuration of Coefficient Table Data ......................................... 165
Coefficient Table Lead Address .......................................................... 165
Most Significant Bit of Coefficient Data .............................................. 166
RAM Control Register ........................................................................ 167
Coefficient Table Control Register ...................................................... 168
Coefficient Table Address Offset Register .......................................... 170
Chapter 7 Line Screen .............................................................................................. 171
Introduction..................................................................................................... 172
7.1 Line Color Screen .................................................................................... 172
Line Color Screen Table Address Register ......................................... 174
7.2 Back Screen ............................................................................................. 175
Back Screen Table Address Register ................................................. 176
Chapter 8 Windows ................................................................................................... 179
8.1 Window Area ............................................................................................ 180
Normal Rectangular Window .............................................................. 180
Window Position Register .................................................................. 181
Normal Line Window .......................................................................... 184
Line Window Table Address Register ................................................. 186
Sprite Window .................................................................................... 187
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Sprite Control Register ....................................................................... 188
Window's Active Area for the Screen.................................................. 189
8.2 Window Process .......................................................................................190
Window Control Register .................................................................... 193
Chapter 9 Sprite Data ...............................................................................................199
9.1 Sprite Data ...............................................................................................200
Sprite Types ........................................................................................ 200
Sprite Color Mode............................................................................... 203
9.2 Priority and Color Calculation ................................................................... 204
Priority Number Selection ................................................................... 204
Color Calculation Enable Conditions .................................................. 205
Color Calculation Ratio Selection ....................................................... 206
Sprite Control Register ....................................................................... 207
Priority Number Register .................................................................... 209
Color Calculation Ratio Registers ...................................................... 210
Chapter 10 Pixels ...................................................................................................... 213
Introduction..................................................................................................... 214
10.1 Palette Format Pixels ............................................................................. 214
Sprite Dot Pixels ................................................................................. 214
Scroll Dot Pixels ................................................................................. 216
Color RAM Address Offset Register ................................................... 217
10.2 RGB Format Pixels ................................................................................ 218
Sprite Pixels........................................................................................ 218
Scroll Pixels ........................................................................................ 218
10.3 Special Function Code ........................................................................... 220
Special Function Code Select Register .............................................. 221
Special Function Code Register ......................................................... 222
Chapter 11 Priority Function ......................................................................................223
Introduction..................................................................................................... 224
11.1 Priority Function ......................................................................................224
Priority Number ................................................................................... 224
Priority Number Register .................................................................... 225
11.2 Special Priority Function ......................................................................... 227
Special Priority Mode Register ........................................................... 229
11.3 Insertion of Line Color Screen ............................................................... 230
Line Color Screen Enable Register .................................................... 231
Chapter 12 Color Calculations ................................................................................... 233
Introduction..................................................................................................... 234
12.1 Color Calculation Function ..................................................................... 234
Normal Color Calculation ................................................................... 234
Extended Color Calculation Function ................................................. 236
12.2 Gradation Calculation Function .............................................................. 238
Color Calculaton Control Register ...................................................... 240
Color Calculation Ratio Register ........................................................ 243
12.3 Special Color Calculation Function ........................................................ 245
Special Color Calculation Mode Register ........................................... 247
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Chapter 13 Color Offset Function ............................................................................. 249
Introduction..................................................................................................... 250
13.1 Color Offset Selection ............................................................................ 250
Color Offset Enable Register .............................................................. 251
Color Offset Select Register ............................................................... 252
Color Offset Register .......................................................................... 253
Chapter 14 Shadow Function ................................................................................... 255
Introduction..................................................................................................... 256
14.1 Shadow Process .................................................................................... 256
Normal Shadow .................................................................................. 256
MSB Shadow ......................................................................................258
Shadow Control Register ................................................................... 259
Chapter 15 How to Use VDP2 .................................................................................. 261
15.1 Operation Flow ....................................................................................... 262
15.2 How to Use RAM .................................................................................... 264
15.3 Bit Configuration Map ............................................................................. 267
Chapter 16 Quick Reference .................................................................................... 295
16.1 Register Map .......................................................................................... 296
16.2 Register Bit List ......................................................................................315
16.3 Register Bit Functions ............................................................................ 328
16.4 Table List ................................................................................................389
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Table of Figures
Chapter 1 VDP2 Functions
Figure 1.1 System Configuration ........................................................................ 2
Figure 1.2 Address Map ..................................................................................... 3
Chapter 2 TV Screen
Figure 2.1 Display Method by Interlace Setting ............................................... 14
Figure 2.2 TV Screen Structure........................................................................ 15
Chapter 3 RAM
Figure 3.1 Different Capacities of VRAM Address Map ................................... 27
Figure 3.2 VRAM Cycle Pattern Register ......................................................... 32
Figure 3.3 Access Selection Limits of Pattern Name Table Data ..................... 33
Figure 3.4 Example of Character Pattern Data Read Access
Selection ......................................................................................... 34
Figure 3.5 Access Select Limits of Vertical Cell Scroll Table Data ................... 35
Figure 3.6 CPU Read/Write Access Selection when
VRAM is not Divided into Two Bank ............................................... 36
Figure 3.7 CPU Read/Write Access Selection when
VRAM is Divided into Two Banks ................................................... 37
Figure 3.8 VRAM Cycle Pattern Selection ....................................................... 39
Figure 3.9 Color Data Configuration on Color RAM ......................................... 44
Figure 3.10 Color Data of the Color RAM ........................................................ 45
Chapter 4 Scroll Screen
Figure 4.1 Scroll Screen Configuration of Cell Format ..................................... 50
Figure 4.2 Scroll Screen Configuration of Cell Format and
Corresponding Data Settings ......................................................... 51
Figure 4.3 Scroll Screen Configuration of Bit Map Format............................... 52
Figure 4.4 Relationship of bit map format scroll screen and data settings ....... 52
Figure 4.5 Configuration of Cells by Character Color Count ............................ 54
Figure 4.6 RGB Format Dot Data ..................................................................... 58
Figure 4.7 Cell Arrangement by Character Size ............................................... 59
Figure 4.8 Data Configuration of Pattern Name Tables ................................... 65
Figure 4.9 Bit Configuration when Pattern Name Data is 2 Word .................... 69
Figure 4.10 Configuration when Pattern Name Data is 1 Word ....................... 71
Figure 4.11 Dot Color Data by Character Number of Colors ............................ 74
Figure 4.12 Reverse Display of Character Patterns ......................................... 75
Figure 4.13 Arrangement of Pattern Name Table by Plane Size ...................... 79
Figure 4.14 Map Selection Register ................................................................. 82
Figure 4.15 Map Size ....................................................................................... 84
Figure 4.16 Plane Arrangement of Map by Reduction Settings ....................... 85
Figure 4.17 Bit Map Pattern Configuration ....................................................... 96
Figure 4.18 Dot Color Data by Bit Map Number of Colors ............................. 111
Figure 4.19 Mosaic Pattern ............................................................................ 117
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Chapter 5 Normal Scroll Screen
Figure 5.1 Screen Scroll Value Bit Configuration ........................................... 122
Figure 5.2 Configuration of Coordinate Increment Register........................... 126
Figure 5.3 Line Scroll Function ...................................................................... 131
Figure 5.4 Bit Configuration of Line Scroll Table Data ................................... 132
Figure 5.5 Line Scroll Table ............................................................................ 133
Figure 5.6 Vertical Cell Scroll Function .......................................................... 134
Figure 5.7 Data Configuration on Vertical Cell Scroll Table ........................... 135
Figure 5.8 Vertical Cell Scroll Table................................................................ 136
Chapter 6 Rotation Scroll Screen
Figure 6.1 Rotation Scroll Screen Display Method ........................................ 145
Figure 6.2 Rotation Parameter data Configuration ........................................ 153
Figure 6.3 Rotation Parameter Table ............................................................. 156
Figure 6.4 How to Store to the Rotation Parameter Table VRAM .................. 157
Figure 6.5 Rotation Parameter Change ......................................................... 161
Figure 6.6 Line Color Screen Data Using Coefficient Data ............................ 164
Figure 6.7 Bit Configuration of Coefficient Table Data ................................... 165
Chapter 7 Line Screen
Figure 7.1 Line Screen ................................................................................... 172
Figure 7.2 Configuration of Line Color Screen Table ..................................... 173
Figure 7.3 Bit Configuration of Line Color Screen Table Data ....................... 173
Figure 7.4 Configuration of Back Screen Table .............................................. 175
Figure 7.5 Bit Configuration of Back Screen Table Data ................................ 176
Chapter 8 Windows
Figure 8.1 Normal Rectangle Window ........................................................... 180
Figure 8.2 Normal Line Window ..................................................................... 184
Figure 8.3 Bit Configuration of Normal Line Window Table Data ................... 184
Figure 8.4 Configuration of Normal Line Window Table ................................. 185
Figure 8.5 Sprite Window ............................................................................... 187
Figure 8.6 Active Area of Windows ................................................................ 189
Figure 8.7 Window Process ........................................................................... 191
Chapter 9 Sprite Data
Figure 9.1 Sprite Types .................................................................................. 201
Chapter 10 Dot Color Data
Figure 10.1 Palette Format Sprite Dot Color Data ......................................... 215
Figure 10.2 Sprite Color RAM Address .......................................................... 215
Figure 10.3 Palette Format Scroll Dot Color Data .......................................... 216
Figure 10.4 Scroll Color RAM Address .......................................................... 216
Figure 10.5 RGB Format Sprite Dot Color Data ............................................. 218
Figure 10.6 RGB Format Scroll Dot Color Data ............................................. 219
Figure 10.7 Dot Color Code Corresponding to Special Function Code ......... 220
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Chapter 11 Priority Function
Figure 11.1 Priority Function .......................................................................... 224
Figure 11.2 Line Color Screen Insertion ......................................................... 230
Chapter 12 Color Operations
Figure 12.1 Color Calculation Function ......................................................... 234
Figure 12.2 Color Calculation Ratio Mode ..................................................... 236
Figure 12.3 Expand Color Operation Function ............................................... 237
Figure 12.4 Gradation Calculation Function ................................................... 239
Chapter 13 Color Offset Function
Figure 13.1 Color Offset Data ........................................................................ 250
Chapter 14 Window Function
Figure 14.1 Shadow Function ........................................................................ 256
Figure 14.2 Sprite Data Write of a Normal Shadow ....................................... 257
Figure 14.3 Sprite Data of a Normal Shadow ................................................ 257
Figure 14.4 Sprite Shadow and Transparent Shadow ................................... 258
Figure 14.5 Sprite Data of MSB Shadow ....................................................... 259
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List of Tables
Chapter 1 VDP2 Functions
Table 1.1 TV Screen Mode ................................................................................. 5
Table 1.2 Scroll Screen ..................................................................................... 5
Table 1.3 Windows ............................................................................................. 6
Table 1.4 Scroll Screen Function ....................................................................... 6
Chapter 2 TV Screen
Table 2.1 TV Screen Mode ............................................................................... 12
Table 2.2 Register for Setting the External Screen .......................................... 21
Table 2.3 H Counter Register Bit Content ........................................................ 24
Table 2.4 V Counter Register Bit Content ........................................................ 24
Chapter 3 RAM
Table 3.1 Data Defined in VRAM ..................................................................... 26
Table 3.2 Access Numbers of Required Pattern Name Table Data
during 1 Cycle .................................................................................. 33
Table 3.3 Character Pattern Data (Bit Map Pattern Data)
Read Access Number ...................................................................... 34
Table 3.4 Character Pattern Data Read Access Selection Limits .................... 34
Table 3.5 Access Command ............................................................................. 40
Chapter 4 Scroll Screen
Table 4.1 Character Color Count and Dot Data Size ....................................... 53
Table 4.2 Cell Data Configuration .................................................................... 53
Table 4.3 Transparent Dot Data Values ........................................................... 58
Table 4.4 Pattern Name Table Capacity Page Boundary of One Page ............ 64
Table 4.5 Character Number Auxiliary Mode .................................................... 69
Table 4.6 Bit Configuration when Pattern Name Table is 1 Word .................... 70
Table 4.7 Reverse Function Bit ........................................................................ 75
Table 4.8 Address Value of Map Designation Register by Setting ................... 83
Table 4.9 Bit Map Size ..................................................................................... 93
Table 4.10 Bit Map Color Count ....................................................................... 94
Table 4.11 Bit Map Pattern Capacity per Surface ........................................... 95
Table 4.12 Normal Scroll Screen Display Area .............................................. 114
Table 4.13 Rotation Scroll Screen Display Area ............................................. 114
Chapter 5 Normal Scroll Screen
Table 5.1 Horizontal Coordinate Increment and Reduction Setting ............... 128
Table 5.2 Display Screen Limits by Setting of Reduction Enable Bit ............. 130
Chapter 6 Rotation Scroll Screen
Table 6.1 Rotation Scroll Screen ................................................................... 144
Table 6.2 Rotation Parameters ....................................................................... 151
Table 6.3 Lease significant bit of Coefficient Parameter
Data Showing the Address Value Separate from
Coefficient Parameter Data Size ..................................................... 166
Table 6.4 Image Processing using RGB0 Coefficient Data MGB Value. ........ 167
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Chapter 8 Windows
Table 8.1 Bit Content of Window Position Register for Horizontal
Coordinates. .................................................................................... 182
Table 8.2 Bit Content of Window Position Register for Vertical
Coordinates. .................................................................................... 183
Chapter 9 Sprite Data
Table 9.1 Shared Bits ..................................................................................... 200
Table 9.2 Selection of Sprite Priority Number Register .................................. 204
Table 9.3 Selection of Sprite Color Calculation Ratio Register ...................... 206
Chapter 11 Priority Function
Table 11.1 Priority when the Priority Numbers are Equal ............................... 225
Table 11.2 Special Priority Function by Mode ................................................ 228
Chapter 12 Color Operation
Table 12.1 Color Operation Function when in High Resolution
Mode or Special Monitor Mode .................................................... 236
Table 12.2 Expanded Color Calculation Ratio................................................ 238
Table 12.3 Special Color Calculation Mode ................................................... 246
Chapter 15 Method of Using VDP2
Table 15.1 Register Connected with Data Defined in VRAM ......................... 265
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Chapter 1 VDP2 Functions
Introduction .......................................................... 2
1.1
System Configuration .................................. 2
1.2
Address Map ............................................... 3
VRAM .................................................... 3
Color RAM ............................................. 3
Register ................................................. 4
1.3
Scroll Function ............................................ 5
Display Screen ...................................... 5
Scroll Screen ......................................... 6
Line Screen .......................................... 7
Windows
.......................................... 7
1.4
Priority Function .......................................... 8
Priority Function .................................... 8
Color Calculation Function .................... 8
Color Offset Function ............................ 8
Shadow Function ................................... 9
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Introduction
VDP2 has a scroll and priority function. The scroll function defines the scroll screen,
moves the screen up, down, right, left, and rotates the screen. The priority function
prioritizes the display of multiple scroll screens, sprites, and external screens. It also
processes the images in operations such as color calculation and color offset.
1.1 System Configuration
VDP2 is connected to 4 Mbit or 8 Mbit VRAM and contains 32K bits of color RAM.
Image data is defined in the VRAM and color RAM from the CPU via the SCU.
Image display controlling information is set by each register in the same way. Data
defined by VRAM is read according to the setting of the register, then becomes the
image data of each scroll screen. Image data of each scroll screen and sprite image
data received from VDP1, as well as the external image data received from outside,
become image display data. Display priority is decided by the register setting.
When display image data is in a palette format, color data defined in the color RAM
according to that value is read and displayed. When display image data is in the
RGB format, it is shown as is. In this way, the acquired display color data is output
to the display device. The VDP2 system configuration is shown in Figure 1.1.
VDP2
Register
Color RAM
VRAM
Display Device
SCU
CPU
VDP1
External Screen
Circuitry
(OPTION)
Figure 1.1 System Configuration
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1.2 Address Map
In order to define pattern name tables and character pattern data, VDP2 is connected
to two VRAMs. VDP2 contains 32K bits of color RAM for defining color data, and
together with internal registers control VRAM. Figure 1.2 shows VDP2 controlled
VRAM, color RAM, and register address maps.
000000H
VRAM
COLOR-RAM
REGISTER
0FFFFFH
100000H
17FFFFH
180000H
1BFFFFH
Figure 1.2 Address Map
VRAM
VRAM stores scroll screen image data and data tables needed in each function.
Read access by VDP2 is always given priority over read/write access through the
CPU or DMA controller. Consequently, the wait cycle enters the CPU or DMA
controller through the access timing. Access through the CPU or DMA controller is
possible in units of byte, word, and long word.
Color RAM
Color RAM stores color data of sprites and scroll screens. It also defines the enable
bit of the color calculation function as it applies to the most significant bit when
necessary. Read/write access from the CPU or DMA controller is possible, but the
image may be disturbed by the access timing. Access through the CPU or DMA
controller is possible only in word units and long word units. Access in bytes is not
allowed.
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Register
Registers set each VDP2 function. Because the values of most registers are cleared to
0 after power on or reset, the values must be set. Read/write access from the CPU or
DMA controller is always possible, but the image may be poor due to the access
timing. Access by the CPU or DMA controller is possible only in word units and
long word units. Access in bytes is not allowed.
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1.3 Scroll Function
The VDP2 scroll function has a scroll screen and a window.
Display Screen
The TV screen mode has the following characteristics.
Table 1.1 TV Screen Mode
The scroll screen which can be displayed has the following characteristics.
Table 1.2 Scroll Screen
Scroll Screen Name
Name
Remarks
Normal Scroll 0
NBG0
Can move up/down/left/
Normal
Normal Scroll 1
NBG1
right. Can scale
Scroll Screen
Normal Scroll 2
NBG2
Can move up/down/left/
Normal Scroll 3
NBG3
right.
Rotation
Rotation Scroll 0
RBG0
Can scale/rotate
Scroll Screen
Rotation Scroll 1
RBG1
Line
Line Color Screen
LNCL
Used only in color
calculations
Screen
Back Screen
BACK
Displayed only when
other screens are not
displayed
Expandable Screen
External Input Screen
EXBG
Screen input externally
TV Screen
M o d e
Graphic Mode
Horizontal
Resolution
(Pixels)
Vertical
Resolution
(Pixels)
Display Device
Normal
Normal
Graphic A
320
224
NTSC Format
Normal
Graphic B
352
240
or
Hi-Res
Hi-Res
Graphic A
640
256
PAL Format
Hi-Res
Graphic B
704
selection
TV
Exclusive Normal
Graphic A
320
480
31kHz Monitor
Exclusive
Exclusive Normal
Graphic B
352
480
Hi-Vision Monitor
Monitor
Exclusive Hi-Res
Graphic A
640
480
31kHz Monitor
Exclusive Hi-Res
Graphic B
704
480
Hi-Vision Monitor
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The following windows exist:
Table 1.3 Windows
Scroll Screen
The functions of the scroll screen are listed in the table below.
Table 1.4 Scroll Screen Function
Note:
*There are 2048 colors when the color RAM is in mode 1, and 1024 colors when in mode
0 or 2.
Normal scroll screen changes the number of screens that can be displayed through
each setting.
Window Name
Name
Remarks
Normal Window
W 0
Line Window allowed
W 1
Sprite Window
SW
Sprite Character Window
Function
Normal Scroll Screen
Rotation Scroll Screen
NBG0
NBG1
NBG2
NBG3
RBG0
RBG1
Character
Color Count
16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors
selection
16 colors
256 colors
2048 colors
32,768 colors
selection
16 colors
256 colors
selection
16 colors
256 colors
selection
16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors
selection
16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors
selection
Character
Size
1 Cell H x 1 Cell V; 2 Cells H x 2 Cells V
Pattern Name
Data Size
1 Word, 2 Words selection
Plane Size
1 H x 1 V 1 Pages; 2 H x 1 V 1 Pages; 2 H x 2 V Pages
Plane Count
4
4
4
4
16
16
Bitmap
Display
Display
Allowed
Display
Allowed
Display Not
Allowed
Display Not
Allowed
Display
Allowed
Display Not
Allowed
Bitmap Size
512 H x 256 V Dots
512 H x 512 V Dots
1024 H x 256 V Dots
1024 H x 512 V Dots
selection
None
512 H X 256 V
Dots
512 H X 512 V
selection
None
Scale
Function
1/4~256 ratio
None
Any Ratio
Rotation
Function
None
Yes
Line Scroll
Function
Yes
Yes
No
No
No
Vertical Cell
Scroll Function
Yes
Yes
No
No
No
Mosaic
Process
Function
Yes
Yes
(Horizontal Direction Only)
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The normal scroll screen can be displayed simultaneously with one rotation scroll
screen. If two rotation scroll screens are displayed, the normal scroll screen cannot
be displayed (the register that sets RBG1 is used for NBG0). When an external input
screen is displayed, NBG1 cannot be displayed. The register setting the external
input screen can be used for NBG1.
Line Screen
The line color screen works for color calculation and on other screens. It can indicate
whether the entire screen consists of one color, or if there is a color for each line, but
it cannot display characters.
The back screen is displayed when all other screens are transparent. The entire
screen is displayed in one color, or a color can be selected for each line, but charac-
ters cannot be displayed.
Windows
A rectangular window can be selected by using the two screen coordinate value
points in the upper left and lower right corners of a normal window. The sprite
window is a window based on sprite characters. There are three types of windows
that can be used and stacked individually for each screen: the "transparent control
window" designates the transparent area; the "color calculation window" designates
the area in which color calculation is not performed; the "rotation parameter win-
dow" changes screens by two rotation parameters.
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1.4 Priority Function
There are four types of VDP2 priority functions: priority function, color calculation
function, color offset function, and shadow function.
Priority Function
The display priority of the sprite and scroll screen is decided by a 3-bit priority
number. The sprite priority number can be set at a maximum value of 8, one of
which is designated by character units. The scroll screen priority number is usually
designated by surface units. When the special priority function is used, character
units and dot units can change the scroll screen priority number.
Color Calculation Function
By adding color data of multiple screens, the color calculation function produces an
effect in which the back screen can be seen through the front screen. It is normally
performed by two screen images, the top image and the second image, but up to
four screens can be peformed when the expanded color calculation function is used.
Surface units determine whether the color calculation is performed. Sprites can be
selected by character units through sprite color calculation condition settings. When
a scroll screen uses the special color calculation function, sprites can be selected by
character units and dot units.
The color calculation ratio of the top and second images can be selected from 32
steps. Sprites can set a maximum of 8 color calculation ratios, among which one can
be selected by character units. The scroll screen is selected by surface units.
When the Gradation function is used, one selected screen can be gradated horizon-
tally and displayed.
Color Offset Function
The color offset function is used for displaying the offset value calculation (subtrac-
tion) for color data, and for fade in and fade out purposes. The color offset function
can be specified by surface unit. Up to two color offset values can be selected for
each RGB, one of which can be specified by surface units.
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Shadow Function
The shadow function adds shadow to the shapes of sprite characters on each screen.
There are two types of sprite shadow: normal shadow by data, and MSB shadow.
The normal shadow can only add a shadow to the scroll screen. The MSB shadow
can add a shadow to scroll screens and to sprites.
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(This page was blank in the original Japanese document.)
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Chapter 2 TV Screen
2.1
TV Screen Mode .................................................. 12
Special High Resolution Graphics Mode ............. 13
2.2
Interlace Mode ..................................................... 14
2.3
TV Screen Structure ............................................ 15
2.4
TV Screen Mode Register ................................... 16
2.5
External Signals and Scan Conditions ................ 19
External Signal Enable Register .................... 19
Screen Status Register .................................. 21
H Counter Register ........................................ 23
V Counter Register ........................................ 24
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2.1 TV Screen Mode
VDP2 can display images in 31 kHz monitors as well as high-vision monitors, and in
NTSC and PAL standards for TV. There are three kinds of image displaying TV
screen modes: normal, high-resolution, and special monitor. Screen scan format can
be selected from three types: non-interlace, single-density interlace, and double-
density interlace. A register showing TV scan conditions is also provided.
Table 2.1 shows the TV screen modes that are selectable, the graphics mode, and the
current resolution. Furthermore, special settings are required when indicating
special high-resolution graphics A and special high-resolution graphics B.
Table 2.1 TV Screen Mode
TV Screen
M o d e
Graphics Mode
Interlace Mode
Horiz X Vertical.
Resolution
(Pixels)
Restrictions During
Use
Normal
320 X 224
Non-interlace
320 X 240
Normal
320 X 256
PAL standard only
Graphic A
320 X 448
Interlace
320 X 480
320 X 512
PAL standard only
352 X 224
Non-interlace
352 X 240
Normal
352 X 256
PAL standard only
Graphic B
352 X 448
Interlace
352 X 480
352 X 512
PAL standard only
Hi-Res
640 X 224
Non-interlace
640 X 240
Hi-Res
640 X 256
PAL standard only
Graphic A
640 X 448
Interlace
640 X 480
640 X 512
PAL standard only
704 X 224
Non-interlace
704 X 240
Hi-Res
704 X 256
PAL standard only
Graphic B
704 X 448
Interlace
704 X 480
704 X 512
PAL standard only
Non-interlace
320 X 480
31kHz monitor only
Non-interlace
352 X 480
Hi-vision monitor only
Non-interlace
640 X 480
31kHz monitor only
Non-interlace
704 X 480
Hi-vision monitor only
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Special High-Resolution Graphics Mode
The graphics mode of special high-resolution graphics A or B displays one screen by
joining the NBG0 and NBG1 screens. If the following setting is not performed, the
display will not appear correctly.
Must be able to display only NBG0 and NBG1.
The NBG0 and NBG1 character pattern tables (or, bit map pattern) and pattern
name tables must use the exact same data.
Must be able to reduce both NBG0 and NBG1 horizontally up to 50%.
Set the vertical direction screen scroll values of NBG0 and NBG1 so that they
are identical.
Set the NBG1 horizontal screen scroll value at the NBG0 horizontal screen
scroll value plus 1.
Set both NBG0 and NBG1 horizontal coordinate increments at 2.
Set the color RAM mode to 0.
Set the priority numbers of NBG0 and NBG1 at the same value.
Do not enter the line color screen.
Special priority of both NBG0 and NBG1 should be in mode 0.
Do not use the color calculation function.
For registers other than those listed above, NBG0 and NBG1 settings should
be the same.
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2.2 Interlace Mode
VDP2 interlace mode (screen scan method) consists of non-interlace, single-density
interlace, and double-density interlace modes. The non-interlace mode is 1 field per
frame (1/60 sec.). The single-density interlace mode is 2 fields (1/30 sec.) per frame;
the same image is displayed in even and odd fields. The double-density interlace
mode is 2 fields (1/30 sec.) per 1 frame with separate images being displayed in even
and odd fields. There is no space between scan lines in both the single-density and
double-density interlace modes, but the actual resolution in the vertical direction of
the single-density interlace mode is the same as the resolution in the vertical direction
of the non-interlace mode. Figure 2.1 shows display methods by interlace settings.
Figure 2.1 Display Method by Interlace Setting
q
Singl e Densi ty I nt erl ace Mod e
q
Doub le Den sit y Inter lace Mo de
Sca nn in g occu rs i n ea ch o dd an d even field ,
ho weve r, sin ce the same pi cture is di sp la yed , the
vertica l resol utio n wi ll be si milar to that in the N on-
Interl ace M ode .
1 frame p er 2 fiel ds (1/30 se c.)
Be cau se sca nn ing occu rs a t the same a rea i n
eve ry fiel d, some area s may n ot be scan ne d, thu s
crea ting some g ap s.
1 frame p er 1 fiel d (1/60 se c.)
Sca nn in g occu rs i n ea ch o dd an d even field ,
ho weve r, sin ce di fferent pi ctures are di spl ayed ,
the ve rtica l resol ution wil l b e d ou bl e tha t in the
Non -Interlace mod e.
1 frame p er 2 fiel ds (1/30 se c.)
8X8 Do t Char act er Pat ter n
q
No n- Inter lace Mo de
8X8 Do t Char act er Pat ter n
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2.3 TV Screen Structure
In response to the TV screen mode, VDP2 outputs image signals corresponding to
their respective NTSC standard or PAL standard TV, 31 kHz monitor, and high-
vision monitor. The TV screen is a collection of rasters constructed by vertical dis-
play intervals, vertical blank intervals (V blank interval), and their respective hori-
zontal display intervals and horizontal blank intervals (H blank interval). The TV
screen structure is shown in Figure 2.2. The location where horizontal display inter-
vals and vertical display intervals overlap is the standard display area of the various
TV formats. The set display area, where VDP2 is able to display the image, is
slightly smaller than the standard display area. The border area excludes the set
display area from the standard display, and can output either black or the back
screen.
Boar de r A re a
Set ting
Displ ay Are a
Hor izo nt al Tr acin g
Per iod
Stand ar d Displ ay A re a= Setting Displ ay Area+ Boar de r Area
Stan da rd
Displ ay Are a
Ho rizo nt al Disp lay
Per iod
Hor izon tal Tra ci ng
Per iod
Ver tica l Traci ng
Peri od
Ve rtical Displ ay
Per iod
Ver tica l Traci ng
Peri od
Figure 2.2 TV Screen Structure
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2.4 TV Screen Mode Register
The TV screen mode register controls the TV screen display. It is a read/write 16 bit
register and is at address 180000H. After the power on or reset, the value is cleared
to 0 and therefore must be set.
TV screen display bit : Display bit (DISP), bit 15
Controls picture display to the TV screen.
Because it is in the blank condition during the display interval when this bit is 0, the
VRAM can be accessed from the CPU or DMA controller at any time. The colors
displayed when this bit is 0 are selected by the BDCLMD bit. Please make sure to
change this bit from 0 to 1 during V blank.
Border color mode bit (BDCLMD), bit 8
Controls colors displayed by the border area.
Selects colors of all the standard display areas when the DISP bit is 0. However, after
the power on or reset, if this bit is set to 1 without setting DISP bit to 1 even once, the
back screen will not be correctly displayed. When the setting allows the back screen
selection by line, the color displayed in the border area will become the same color
as the lowermost line in the display area.
15
14
13
12
11
10
9
8
TVMD
DISP
~
~
~
~
~
~
BDCLMD
180000H
7
6
5
4
3
2
1
0
LSMD1
LSMD0
VRESO1
VRESO0
~
HRESO2
HRESO1
HRESO0
D I S P
Process
0
Picture is not displayed on TV screen
1
Picture is displayed on TV screen
BDCLMD
Process
0
Displays black
1
Display back screen
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Interlace mode bit (LSMD1, LSMD0) bits 7 and 6
Designates the interlace mode.
Single-density interlace is a mode that shows the same pictures in odd and even
fields; double-density interlace is a mode that shows different pictures in odd and
even fields. In either case, the spaces between scan lines are not vacant. The vertical
resolution for double-density interlace is twice that of non-interlace, but the vertical
resolution of the actual picture for single-density interlace is the same for non-
interlace. Pictures displayed in double-density interlace are vertically half the size
of pictures displayed in single-density interlace or non-interlace. When the horizon-
tal resolution (HRESO2 to HRESO0) setting is in the exclusive monitor mode, make
sure to select the noninterlaced mode (00B).
Vertical resolution bit (VRESO1, VRESO0), bit 5, 4
Designates vertical resolution when a picture is displayed on the TV screen.
Increments when vertical resolution is increased, then are added to the top and
bottom of the screen without changing the screen's center. When set in the special
monitor mode, the horizontal resolution (HRESO2 to HRESO0) is set to 480 lines.
Settings of this bit are ignored.
LSMD1
LSMD0
Process
0
0
Non-Interlace
0
1
Setting not allowed
1
0
Single-density interlace
1
1
Double-density interlace
VRESO1
VRESO0
Vertical Resolution
Display Monitor
0
0
224 Lines
NTSC or PAL format TV
0
1
240 Lines
NTSC or PAL format TV
1
0
256 Lines
PAL format TV
1
1
Not Allowed
-
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Horizontal resolution bit (HRESO2 to HRESO0), bit 2 to 0
Selects the horizontal resolution when a picture is displayed on the TV screen.
When special high-resolution graphics A or B is selected, other registers must be set
as directed. See "Special High Resolution Graphics Mode" on page 13 for more
information. When switching the TV mode from exclusive monitor mode to normal
mode or hi-res mode, make sure to reset the VDP2.
HRESO2
HRESO1
HRESO0
Horizontal
Resolution
Graphic Mode
Display
Monitor
0
0
0
320 Pixels
Normal
Graphic A
0
0
1
352 Pixels
Normal
Graphic B
NTSC
Format or
0
1
0
640 Pixels
Hi-Res
Graphic A
PAL
Format TV
0
1
1
704 Pixels
Hi-Res
Graphic B
1
0
0
320 Pixels
Exclusive Normal
Graphic A
31kHz Monitor
1
0
1
352 Pixels
Exclusive Normal
Graphic B
Hi-Vision Monitor
1
1
0
640 Pixels
Exclusive Normal
Graphic A
31kHz Monitor
1
1
1
704 Pixels
Exclusive Normal
Graphic B
Hi-Vision Monitor
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2.5 External Signals and Scan Conditions
The register controlling external signals has an external signal enable register. The
register displaying TV scan conditions has a screen status register, H counter regis-
ter, and V counter register.
External Signal Enable Register
The external signal enable register controls signals from the VDP2 exterior. It is a
read/write 16 bit register and is at address 180002H. After the power is turned on or
reset, the value is cleared to 0 and must be set.
External latch enable bit (EXLTEN), bit 9
Selects the condition for latching the HV counter value to the HV counter register.
The latched H counter value can read with the H counter register; V counter value
can read with the V counter register. When reading H and V counter values through
external signals such as laser guns, the bit should be set at 1. Otherwise, it should be
set at 0.
EXSYNC enable bit (EXSYEN), bit 8
Controls input to the internal synchronous circuit of the external sync signal.
When synchronizing with other devices and screen displays, set to 1 and input an
EXSYNC signal. The normal setting is 0.
Display area select bit (DASEL), bit1
Designates the image display area. Valid only when the EXBGEN bit is 1.
15
14
13
12
11
10
9
8
EXTEN
~
~
~
~
~
~
EXLTEN
EXSYEN
180002H
7
6
5
4
3
2
1
0
~
~
~
~
~
~
DASEL
EXBGEN
EXLTEN
Condition
0
Latches when reading external signal enable register
1
Latches through external signal
EXSYEN
Process
0
Does not input external sync signal
1
Inputs external sync signal, and synchronizes TV screen display with the
external
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When displaying the entire standard display area, images from external screen data
are displayed correctly. Images not in set display areas (sprite, scroll screen, etc.)
need to be made transparent using a window because they are not displayed cor-
rectly.
EXBG enable bit (EXBGEN), bit 0
Controls input of external screen data.
Because the data becomes NBG1 screen data when inputting external screen data,
the external screen settings are used for NBG1 as well. Table 2.2 shows the register
bit for setting the external screen.
DASEL
Process
0
Displays screen image only in the set display area
1
Displays screen in the standard display area
EXBGEN
Process
0
Does not input external screen data
1
Inputs external screen data
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Table 2.2 Register for setting the external screen
Screen Status Register
The screen status register displays TV screen information. This read exclusive 16-bit
register is at address 180004H.
Address
Bit Number
Bit Name
180020H
9
N1TPON
Transparent display enable
180028H
13,12
N1CHCN1, N1CHCN0
Character Color Count
8
N1W0A
W0 window area
9
N1W0E
W0 window enable
10
N1W1A
W1 window area
1800D0H
11
N1W1E
W1 window enable
12
N1SWA
SW window area
13
N1SWE
SW window enable
15
N1LOG
Window logic
1800E2H
1
N1SDEN
Shadow enable
1800E4H
6~4
N1CAOS2~N1CAOS0
Color RAM address offset
1800E8H
1
N1LCEN
Line color screen insertion enable
1800EAH
3,2
N1SPRM1, N1SPRM0
Special priority mode
1800ECH
1
N1CCEN
Color calculation enable
1800EEH
3,2
N1SCCM, N1SCCM0
Special color calculation mode
1800F8H
10~8
N1PRIN2~N1PRIN0
Priority number
180118H
12~8
N1CCRT4~N1CCRT0
Color Calculation Ratio
180110H
1
N1COEN
Color offset enable
180112H
1
N1COSL
Color offset select
15
14
13
12
11
10
9
8
TVSTAT
~
~
~
~
~
~
EXLTFG
EXSYFG
180004H
7
6
5
4
3
2
1
0
~
~
~
~
VBLANK
HBLANK
ODD
PAL
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External latch flag (EXLTFG), bit 9
Through external signals, this displays whether the HV counter value is latched to
the HV counter register. Clears to 0 when the screen status register reads out.
External SYNC flag (EXSYFG), bit 8
Displays whether the internal routes through External SYNC flag are in sync.
Clears to 0 when the screen status register reads out.
Vertical blank flag (VBLANK), bit 3
Displays the vertical scan status of the TV screen.
Horizontal blank flag (HBLANK), bit 2
Displays the horizontal scan status of the TV screen.
HBLANK
Horizontal Scan Status
0
During horizontal scan
1
During horizontal re-trace (HBLANK)
VBLANK
Vertical Scan Status
0
During vertical scan
1
During vertical re-trace (VBLANK)
E X S Y F G
External Sync Status
0
Not synchronized
1
Internal circuit synchronized
EXLTFG
HV Counter Value Status
0
Not latched in register
1
Latched in register
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Scan Field Flag : Odd/even field flag (ODD), bit 1
Scan conditions are shown when the TV screen mode is the interlace mode. The
non-interlace mode is always 1.
TV standard flags : PAL/NTSC flag (PAL), bit 0
Displays TV standards.
H Counter Register
The H counter register shows the H counter value. This read exclusive 16-bit regis-
ter is at address 180008H.
H counter bit (HCT9 to HCT0), bits 9 to 0
Signals controlled through EXLTEN external signal enable register show the latched
H counter values. The bit configuration of this bit changes according to the setting
of the graphics mode, as seen in Table 2.3. For normal graphics of H counter values,
the HCT0 of the least significant bit is invalid data. For special normal graphics of
H counter values, the HCT9 of the most significant bit is invalid data. For the
H counter value of special high-resolution graphics, the most significant bit of HCT9
becomes invalid. Because there is no bit for H0, it shows a value of 2 dot units.
15
14
13
12
11
10
9
8
HCNT
~
~
~
~
~
~
HCT9
HCT8
180008H
7
6
5
4
3
2
1
0
HCT7
HCT6
HCT5
HCT4
HCT3
HCT2
HCT1
HCT0
O D D
Display
0
During even field scan
1
During odd field scan
PAL
Display
0
NTSC standard
1
PAL standard
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Table 2.3 H counter register bit content
V Counter Register
The V counter register shows the V counter value. This read exclusive 16-bit register
is at address 18000AH.
V counter value bit : V counter bit (VCT9~VCT0), bit 9 to 0
Signals controlled through EXLTEN external signal enable register show the latched
V counter values. The bit configuration of this register changes according to the
settings of the TV screen mode, as shown in Table 2.4. The V counter values for
single density interlace of the normal and high resolution modes show V counter
values in their various even and odd fields. The V counter values for double density
interlace of normal and high resolution modes show the odd fields when 0 and even
field when the least significant bit of VCT0 is 1. VCT1~VCT9 show the V counter
values in their respective fields.
Table 2.4 V counter register bit content
Graphic
Mode
HCT9
HCT8
HCT7
HCT6
HCT5
HCT4
HCT3
HCT2
HCT1
HCT0
Normal
H8
H7
H6
H5
H4
H3
H2
H1
H0
Invalid
Hi-Res
H9
H8
H7
H6
H5
H4
H3
H2
H1
H0
Exclusive
Normal
Invalid
H8
H7
H6
H5
H4
H3
H2
H1
H0
Exclusive
Hi-Res
Invalid
H9
H8
H7
H6
H5
H4
H3
H2
H1
15
14
13
12
11
10
9
8
VCNT
~
~
~
~
~
~
VCT9
VCT8
18000AH
7
6
5
4
3
2
1
0
VCT7
VCT6
VCT5
VCT4
VCT3
VCT2
VCT1
VCT0
TV Screen
(Interlace) Mode
VCT9
VCT8
VCT7
VCT6
VCT5
VCT4
VCT3
VCT2
VCT1
VCT0
Normal Hi-Res
(Non-Interlace,
Single-Density
Interlace)
V8
V7
V6
V5
V4
V3
V2
V1
V0
Invalid
Normal Hi-Res
(Double-Density
Interlace)
V8
V7
V6
V5
V4
V3
V2
V1
V0
0: Odd fields
1: Even fields
Exclusive
Monitor
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
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Chapter 3 RAM
Introduction...................................................................... 26
3.1 Address Map ............................................................. 26
VRAM Size Register ............................................... 28
3.2 VRAM Bank Partitioning ............................................ 29
RAM Control Register ............................................ 29
3.3 Accessing VRAM During Display Interval ................. 31
VRAM Access During Display Interval ................... 31
Image Data Access ................................................ 32
Vertical Cell Scroll Table Data Access .................... 35
Read/Write Access by the CPU .............................. 35
VRAM Cycle Pattern Selection Process................. 37
VRAM Cycle Pattern Register ................................ 39
3.4 Color RAM Mode ....................................................... 43
RAM Control Register ............................................ 45
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Introduction
VDP2 is connected to special VRAM for defining pattern name tables, character
patterns, and so on. VRAM has two divisions called VRAM-A and VRAM-B, each
having equal capacity. VRAM-A and VRAM-B can each be divided into two banks,
called bank 0 and bank 1. Banks divided with four equal capacities are called
VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. VRAM data is defined in table
3.1. Also contained is color RAM for defining the color data of scroll screens and
sprites.
Table 3.1 Data defined in VRAM
3.1 Address Map
VDP2 can be applied to two types of VRAM: 4 Mbit and 8 Mbit. Programs created
for systems using a 4 Mbit VRAM can also be used in systems using 8 Mbit VRAM,
but programs created for systems using an 8 Mbit VRAM cannot be used in systems
using 4 Mbit VRAM.
Data that must be defined when
display format is cell (format)
Data that must be defined when
display format is bitmap (format)
Data defined as necessary
Pattern name table data
Character pattern data
Bitmap pattern data
Line scroll table data
Vertical cell scroll table data
Rotation parameter table data
Coefficient table data
Line color screen table data
Back screen table data
Line window table data
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The address map changes according to VRAM capacity being used in the system, as
shown in Figure 3.1.
q
VRAM Size: 4M Bit
000000H
01FFFFH
VRAM-A0
q
VRAM Size: 8M Bit
VRAM-A0
VRAM-A1
VRAM-B0
VRAM-B1
VRAM-A1
VRAM-B0
VRAM-B1
020000H
03FFFFH
040000H
05FFFFH
060000H
07FFFFH
000000H
03FFFFH
040000H
07FFFFH
080000H
0BFFFFH
0C0000H
0FFFFFH
Figure 3.1 Different Capacities of VRAM Address Map
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VRAM Size Register
The VRAM size register indicates the VRAM capacity to be used in the system. It is
a read/write 16-bit register and is at the 180006H address. Bits 3 to 0 are exclusively
for read only. Because the value of bit15 (VRAMSZ) is cleared to 0 after the power is
turned on or reset, it must be reset.
VRAM size bit (VRAMSZ), bit 15
.
Indicates the VRAM capacity used in the system.
This bit must be set before data is written to VRAM.
Version Number Bit (VER3 to VER0), Bits 3 to 0
Shows the VDP2 version number; the first is 0.
15
14
13
12
11
10
9
8
VRSIZE
VRAMSZ
~
~
~
~
~
~
~
180006H
7
6
5
4
3
2
1
0
~
~
~
~
VER3
VER2
VER1
VER0
VRAMSZ
VRAM Size
0
4 Mbit
1
8 Mbit
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3.2 VRAM Bank Partitioning
VDP2 can access VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1 at the same time
when both VRAM-A and VRAM-B are divided in half. As a result, more image data
can be obtained at once, a higher number of scroll screens can be displayed simulta-
neously, and a screen with multiple colors can be displayed. However, there are
limitations when selecting of VRAM read/write access through the CPU during the
display. Therefore, don't partition the VRAM into two areas when accessing (read/
write) through the CPU during the display. Normally, accessing can be efficiently
done if divided into two areas.
RAM Control Register
RAM control register selects VRAM bank partitions with the objective of using the
rotation scroll screen VRAM as well as the color RAM mode. It is a read/write
16-bit register and is at the 18000EH address. Also, because the value is cleared to 0,
it must be set after the power is turned on or reset.
Color RAM Coefficient Table Enable Bit (CRKTE), Bit 15
See "6.4 Coefficient Table Control."
Color RAM Mode Bit (CRMD1, CRMD0), Bits 13 and 12
See "3.4 Color RAM Mode." Set the Color RAM mode to mode 1 when the CRKTE
bit is 1. At that time, color data can no longer be stored because the second half of
the color RAM (100800H ~ 100FFFH) is used for the coefficient table data.
VRAM Mode Bit (VRBMD, VRAMD), Bits 9 and 8
Controls VRAM bank partitions.
15
14
13
12
11
10
9
8
RAMCTL
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
18000EH
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00
VRAMD
18000EH
Bit 8
For VRAM-A
VRBMD
18000EH
Bit 9
For VRAM-B
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VRxMD
Process
0
Do not partition in 2 banks
1
Partition in 2 banks
Note: Enter A or B into bit name for x.
Rotation Data Bank Select bit: RBG0 DataBank Select Bit (RDBSA00 to RDBSB11), Bits 7 to 0
See "6.2 Rotation Scroll Screen Display Control".
When the CRKTE bit is 1, do not designate to allow the 4 banks of VRAM to be used
as RAM for the coefficient table data.
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3.3 Accessing VRAM During Display Interval
VRAM Access During Display Interval
VDP2 synchronizes scroll screen data with the TV scan and displays them while
reading from VRAM. VRAM access during display repeats the cycle as four or eight
access operating units (1 cycle). When the TV screen mode is the Normal mode, 1
cycle accesses eight times. Also, 1 cycle is accessed four times when in the high-
resolution or special monitor mode. Below are the ten types of VRAM accesses
performed in one cycle:
(1)
Normal scroll screen pattern name data read access.
(2)
Normal scroll screen character pattern data read access or bit map pattern data read access.
(3)
NBG0, NBG1 vertical cell scroll table data read access.
(4)
Read/Write access through the CPU.
(5)
Does not access.
(6)
RGB0 pattern name data read access.
(7)
RGB0 character pattern data read access or bit map pattern data read access.
(8)
RGB0 coefficient table data read access.
(9)
RGB1 pattern name data read access.
(10) RGB1 character pattern data read access.
The timing during the 1 cycle when the above (1) through (5) are performed must be
selected for each bank of VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. This
selection is performed by writing the values of 4 bits, called access commands, to the
VRAM cycle pattern register. Access Commands correspond to the several types of
VRAM access.
Each VRAM access in the above items (6) through (8) occupies a full one cycle,
therefore, for one bank only one type may be selected. This is accomplished by
writing the value corresponding to each VRAM access type to the RAM control
register rotation data bank select bit. The setting of the bank VRAM cycle pattern
register, which select (6) through (8) VRAM access, will become invalid.
Each VRAM access in the above items (9) and (10) occupies a full one cycle. (9) is
fixed in VRAM-B1 and (10) in VRAM-B0. While items (9) and (10) are selected auto-
matically with the display of RGB1, the setting of the VRAM-B0 and VRAM-B1
VRAM cycle pattern registers will become invalid.
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The VRAM cycle pattern register has registers that correspond to the following
banks: VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1. When the VRAM is not di-
vided into two partitions, the VRAM-A0 register is used for VRAM-A, and the
VRAM-B0 register is used for VRAM-B. Registers for VRAM-A1 and VRAM-B1 are
not used. Registers that correspond to the various banks are separated into eight (T0
to T7) access timings. Access is performed in order, beginning from VRAM access,
showing the access command selected in the T0 bit. T0 to T7 are in effect when the
TV screen is in Normal mode, but only T0 to T3 are in effect for the high-resolution
or special monitor mode; T4 to T7 are ignored. Figure 3.2 shows the VRAM cycle
pattern register used during 1 cycle.
Fo r VRAM-A0 (o r VRAM-A )
For VRAM-A 1
Fo r VRAM-B0 (o r VRAM-B )
For VRAM-B 1
Regi st er ena bl ed ran ge (T 0~T 3) in Hi-R es or Excl usive Mon it or Mod e.
1 pa rtition= 4 Bit, sel ect for VRA M access
T0
T1
T2
T3
T4
T5
T6
T7
Re gi st er en abl ed ran ge (T0~ T7) in Norm al Mod e
Figure 3.2 VRAM Cycle Pattern Register
Be sure to set "do not access" for the remaining access time after selecting the VRAM
access required in the display. If the VRAM access address selected in the VRAM
cycle pattern register is not the address in the selected bank, access won't be done
and the correct screen will not be displayed.
Image Data Access
The required image data must be read from VRAM for normal scroll screens (NBG0
to NBG3) to be displayed. When the display format is the cell format, the required
image data is pattern name data and character pattern data. When in a bit map
format, the necessary image data is bit map pattern data . The VRAM access num-
ber for obtaining this image data during 1 cycle is decided by the conditions.
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Pattern name data read access during 1 cycle must be set to a maximum of two
banks, one being either VRAM-A0 or VRAM-B0, and the other being VRAM-A1 or
VRAM-B1. When the VRAM is not divided into two partitions, the VRAM-A0
register is used as VRAM-A, and the VRAM-B0 register is used as VRAM-B; there-
fore, one or the other must be set. Any access timing may be selected if within the
register's effective range in all TV screen modes. The access number must be the
same as the number as determined by conditions, but the related timing does not
need to be selected.
The pattern name data read access number is shown in Table 3.2. The pattern name
data read access selection limits are shown in Figure 3.3.
Table 3.2 Access numbers of required pattern name table data during 1 cycle
T0
T1
T2
T3
T4
T5
T6
T7
Only on e
can be
sel ect ed
Only on e
can be
sel ect ed
For VRA M- A0 (or VRAM- A)
For VRAM-A 1
For VRA M- B0 (or VRAM- B)
For VRAM-B 1
Reg ist er en ab led ra ng e (T0~ T3) in Hi -Res or Excl usi ve Mo ni tor Mo de
Reg ist er en ab led ra ng e (T0~ T7) in No rma l Mo de
Figure 3.3 Access selection limits of pattern name table data
As a rule, the character pattern data read access during 1 cycle can select any timing
from four banks. However, the timing that can be selected through pattern name
data access timing is limited. Only when the pattern name data access of NBG0 and
NBG1 are selected in T0 can select various character pattern data read accesses
through the timings of any of the four banks be selected with are no limits. The
access number must be selected so that it is the same as the number as determined
by the conditions. The related timing does not need to be selected. Character pattern
data read access numbers are shown in Table 3.3. Character pattern data read access
selection limits are shown in Table 3.4.
Item
NBG0~NBG3
Reduction setting
x1
x1/2
x1/4
Number of VRAM
accesses required
during 1 cycle
1
2
4
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T
able 3.3 Character pattern data (bit map pattern data) read access number
Table 3.4 Character pattern data read access selection limits
When the reduction setting is one, all of the character pattern data read access must
observe selection limits if the character pattern data read access is to be two or
greater. If the reduction setting is 1/2 or 1/4, the required access number when the
reduction setting is 1 (one time for 16 colors and two times for 256 colors) must
observe selection limits through one time pattern name data read access. Figure 3.4
shows character pattern data read access selection limits when the pattern name
data read access is selected in T1 and T3, with 256 colors and 1/2 reduction.
T0
T1
T2
T3
T4
T5
T6
T7
For VRAM-A0 (o r VRAM-A )
For VRA M- A1
For VRAM-B0 (o r VRAM-B )
For VRA M- B1
T1 's Pat ter n Na me Dat a Read Access with re spe ct to se le ct ab le ran ge (T0~ T3, T5~T 7)
T3 's Pat ter n Na me Dat a Read Access with re spe ct to se le ct ab le ran ge (T0~ T3, T7)
Not e: Ch ar act er Pattern Dat a Rea d Acce ss must be sel ect ed twice in each se le ct ab le
ran ge.
Figure 3.4 Example of character pattern data read access selection
Item
NBG0~NBG3
Character
Color Count
16
256
2048
32,768
16,770,000
Reduction
setting
1
1/2
1/4
1
1/2
1
1
1
Number of
VRAM
accesses
required
during 1 cycle
1
2
4
2
4
4
4
8
Item
TV Screen
Pattern Name Table Data Access Timing
M o d e
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
Timing that
can select
Normal
T0~T2,
T4~T7
T0~T3,
T5~T7
T0~T3,
T6~T7
T0~T3,
T7
T0~T3
T1~T3
T2,
T3
T3
character
pattern data
access
Hi-Res,
exclusive
monitor
T0~T2
T1~T3
T0, T2,
T3
T0, T1,
T3
-
-
-
-
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Vertical Cell Scroll Table Data Access
When using the vertical cell scroll function in NBG0 and NBG1
{Translator's Note:
The original document reads NB1, we believe this is an error.}
, vertical cell scroll table
data must also be read.
Vertical cell scroll table data read access must be performed for one surface during 1
cycle. Vertical cell scroll table data read access for NBG0 must be selected in T0 or
T1 timing. NBG1 vertical cell scroll table data read access must be selected within
the timing of T0 to T2. Also, access for NBG0 and NBG1 must be by the same bank
and NBG0 access must be selected first.
When specifying the same vertical cell scroll table data read access against multiple
banks, make sure to specify the same access timing.
Figure 3.5 shows access selection limits of vertical cell scroll table data.
T0
T1
T2
T3
T4
T5
T6
T7
NBG0 ver tical scr oll t abl e acce ss sel ect ab le ran ge (T0 , T1)
NBG1 ver tical scr oll t abl e acce ss sel ect ab le ran ge (T0 ~T2 )
For VRA M- A0 (or VRAM-A)
For VRAM-A 1
For VRA M- B0 (or VRAM-B)
For VRAM-B 1
Not e: For NB G0 and NBG1 access timing , NBG0 access must be first sel ect ed in
the sa me bank.
Figure 3.5 Access select limits of vertical cell scroll table data
Read/Write Access by the CPU
When performing read/write access to the VRAM by the CPU during the screen
display interval, the timing must be set to the VRAM cycle pattern register. VDP2
waits for the selected timing in the CPU read/write access when VRAM access is
requested by the CPU, and approves access only in that timing. When read/write
access is not requested by the CPU, nothing will be performed for VRAM, even for
selected timings. Moreover, during read access through the CPU, the wait cycle will
enter the CPU until it is able to read. The write access wait cycle will not be entered
if the two word write access is at least two times.
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VRAM access by the CPU can be selected only in units of access to VRAM-A or
VRAM-B, and can not be selected in bank units.
When selecting VRAM access by the CPU for the VRAM without two partitions, you
should select the CPU read/write access command in the VRAM cycle pattern
register of the timing performing the access. Selecting an access command that does
not access in place of the CPU read/write access command is the same as before. In
the screen display enable register, when the access command (pattern name data
read, character pattern data read, or bit map pattern data read) used for a screen not
set to be displayed is also set, it becomes the CPU read/write access. See "4.1 Screen
Display Control" about the screen display enable register.
When selecting an access command for not to access or CPU read/write with respect
to every access timing of the VRAM that is not partitioned into two areas, the CPU
access will then be always allowed during display period. This allows to use one of
the VRAMs as an auxiliary work RAM. In addition, by switching the VRAM used in
the image display as a frame buffer, the image can be displayed while being rewrit-
ten at a high speed.
Figure 3.6 illustrates the VRAM cycle pattern register selection if CPU read/write
access is being performed in T2 and T4 when VRAM-A is not partitioned.
O the r
Access
Comm an ds
No
Access
CPU Read /
Wri te
VRAM Cycle Pattern
Regi st er f or VRAM-A
T2
T3
T4
T5
O the r
Access
Comm an ds
Figure 3.6 CPU Read/Write Access Selection when VRAM is not Divided into Two Bank
When setting the CPU read/write access for the VRAM that is partitioned into two
areas, the CPU read/write access command must be set in the VRAM cycle pattern
register of both bank 0 and bank 1 of the timing performing access. Further, in the
registers of both bank 0 and bank 1 of the timing before the set CPU read/write
access command timing, the access command that won't access must be selected.
However, when selecting CPU read/write access in linked timing, only the timing
before the lead of the linked access timing may be selected.
Figure 3.7 illustrates the selection of the VRAM cycle pattern register when perform-
ing CPU read/write access linked to T4 and T5 while VRAM-B is divided into two
partitions.
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VRAM Cycle pa ttern Reg ist er
f or VRAM-B0
T3
T4
T5
T6
CPU Rea d/
Wr ite
No A ccess
No A ccess
CPU Re ad /
Writ e
CPU Rea d/
Wri te
CP U Re ad /
Wr it e
O the r
Access
Comm an ds
O the r
Access
Comm an ds
VRA M Cycl e pa ttern Reg ist er
for VRAM-B1
Figure 3.7 CPU Read/Write Access Selection when VRAM is Divided into Two Banks
VRAM Cycle Pattern Selection Process
Selection process to the VRAM cycle pattern register is listed below.
1. Decide the TV screen mode.
2. Decide whether to partition the VRAM into two segments.
3. Decide the number of character colors of the scroll screen being displayed
and the reduction setting. Also, decide whether to use the vertical cell scroll
function.
4. Decide the VRAM bank that will store the required image data (patternname
data, character pattern data, bit map pattern data) for all scroll screens. Decide
the VRAM bank for storing vertical cell scroll table data when the vertical cell
scroll function is used.
5. Decide whether to read/write access through the CPU.
6. To observe selection limits of various access timings, select access command in
the VRAM cycle pattern register.
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An example of VRAM cycle pattern register selection is shown in Figure 3.8.
Set TV screen in normal mode.
Partition both VRAM-A and VRAM-B into two areas.
Set the scroll screen as follows:
For VRAM-A0 (or VRAM-A)
For VRAM-A1
For VRAM-B0 (or VRAM-B)
For VRAM-B1
T0
T1
T2
T3
T4
T5
T6
T7
N1CE
N0CG
N3PN
N0CG
N0PN
N0CG
NA
N0CG
N1PN
N1CG
N1PN
N1CG
N0PN
N1CG
NA
N1CG
NA
NA
NA
NA
CPU
N0CG
CPU
N0CG
CPU
N0CG
CPU
N0CG
NA
NA
N3CG
N3CG
<VRAM CYCLE PATTERN REGISTER>
Screen Name
NBG0
NBG1
NBG3
Pattern Name
A0
A0,A1
A1
Character Pattern
B0,B1
B0,B1
A1,B0
Vertical Cell Scroll Table
-
A0
-
A0: VRAM-A0 A1: VRAM-A1 B0: VRAM-B0 B1: VRAM-B1
Allow CPU read/write access to VRAM-A
Screen Name
NBG0
NBG1
NBG3
Character Colors
256 Colors
Reduction
Setting
x1/2
x1
x1
Vertical Cell Scroll
Function
Do not use
Use
-
Banks that store data per each scroll screen:
<Condition>
256 Colors
256 Colors
N0PN : Pattern name data read for NBG0, N0CG : Character pattern Data Read for NBG
N1PN : Pattern name data read for NBG1, N1CG : Character pattern Data Read for NBG
N3PN : Pattern name data read for NBG3, N3CG : Character pattern Data Read for NBG
N1CE: NBG1 vertical cell scroll table data read, CPU : CPU Read/Write
NA : No access
Figure 3.8 VRAM Cycle Pattern Selection
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VRAM Cycle Pattern Register
The VRAM cycle pattern register controls the VRAM access during the display
interval. It is a 16-bit write only register with addresses from 180010H to 18001EH.
Because the value is cleared to 0 after the power is turned on or reset, it must be
reset.
15
14
13
12
11
10
9
8
CYCA0L
VCP0A03 VCP0A02 VCP0A01 VCP0A00 VCP1A03 VCP1A02 VCP1A01 VCP1A00
180010H
7
6
5
4
3
2
1
0
VCP2A03 VCP2A02 VCP2A01 VCP2A00 VCP3A03 VCP3A02 VCP3A01 VCP3A00
15
14
13
12
11
10
9
8
CYCA0U
VCP4A03 VCP4A02 VCP4A01 VCP4A00 VCP5A03 VCP5A02 VCP5A01 VCP5A00
180012H
7
6
5
4
3
2
1
0
VCP6A03 VCP6A02 VCP6A01 VCP6A00 VCP7A03 VCP7A02 VCP7A01 VCP7A00
15
14
13
12
11
10
9
8
CYCA1L
VCP0A13 VCP0A12 VCP0A11 VCP0A10 VCP1A13 VCP1A12 VCP1A11 VCP1A10
180014H
7
6
5
4
3
2
1
0
VCP2A13 VCP2A12 VCP2A11 VCP2A10 VCP3A13 VCP3A12 VCP3A11 VCP3A10
15
14
13
12
11
10
9
8
CYCA1U
VCP4A13 VCP4A12 VCP4A11 VCP4A10 VCP5A13 VCP5A12 VCP5A11 VCP5A10
180016H
7
6
5
4
3
2
1
0
VCP6A13 VCP6A12 VCP6A11 VCP6A10 VCP7A13 VCP7A12 VCP7A11 VCP7A10
15
14
13
12
11
10
9
8
CYCB0L
VCP0B03 VCP0B02 VCP0B01 VCP0B00 VCP1B03 VCP1B02 VCP1B01 VCP1B00
180018H
7
6
5
4
3
2
1
0
VCP2B03 VCP2B02 VCP2B01 VCP2B00 VCP3B03 VCP3B02 VCP3B01 VCP3B00
15
14
13
12
11
10
9
8
CYCB0U
VCP4B03 VCP4B02 VCP4B01 VCP4B00 VCP5B03 VCP5B02 VCP5B01 VCP5B00
18001AH
7
6
5
4
3
2
1
0
VCP6B03 VCP6B02 VCP6B01 VCP6B00 VCP7B03 VCP7B02 VCP7B01 VCP7B00
15
14
13
12
11
10
9
8
CYCB1L
VCP0B13 VCP0B12 VCP0B11 VCP0B10 VCP1B13 VCP1B12 VCP1B11 VCP1B10
18001CH
7
6
5
4
3
2
1
0
VCP2B13 VCP2B12 VCP2B11 VCP2B10 VCP3B13 VCP3B12 VCP3B11 VCP3B10
15
14
13
12
11
10
9
8
CYCB1U
VCP4B13 VCP4B12 VCP4B11 VCP4B10 VCP5B13 VCP5B12 VCP5B11 VCP5B10
18001EH
7
6
5
4
3
2
1
0
VCP6B13 VCP6B12 VCP6B11 VCP6B10 VCP7B13 VCP7B12 VCP7B11 VCP7B10
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40
Table 3.5 shows access command that corresponds to the content of the VRAM
access during 1 cycle.
Table 3.5 Access command
Note:
n: 0 to 7 (corresponds to access timing T0 to T7)
xx: A0, A1, B0, B1 (corresponds to VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1)
VRAM cycle pattern (for VRAM-A0) bit: VRAM cycle pattern bit (VCP0A00 to VCP0A03,
VCP1A00 to VCP1A03, VCP2A00 to VCP2A03, VCP3A00 to VCP3A03, VCP4A00 to VCP4A03,
VCP5A00 to VCP5A03, VCP6A00 to VCP6A03, VCP7A00 to VCP7A03)
Sets the access command of VRAM access that performs in VRAM-A0 (or VRAM-A)
timing T0 to T7.
Access Command Value
VRAM Access
VCPnxx3
VCPnxx2
VCPnxx1
VCPnxx0
0
0
0
0
NBG0 Pattern Name Data Read
0
0
0
1
NBG1 Pattern Name Data Read
0
0
1
0
NBG2 Pattern Name Data Read
0
0
1
1
NBG3 Pattern Name Data Read
0
1
0
0
NBG0 Character Pattern Data Read
0
1
0
1
NBG1 Character Pattern Data Read
0
1
1
0
NBG2 Character Pattern Data Read
0
1
1
1
NBG3 Character Pattern Data Read
1
0
0
0
Setting not allowed
1
0
0
1
Setting not allowed
1
0
1
0
Setting not allowed
1
0
1
1
Setting not allowed
1
1
0
0
NBG0 Vertical Cell Scroll Table Data Read
1
1
0
1
NBG1 Vertical Cell Scroll Table Data Read
1
1
1
0
CPU Read/Write
1
1
1
1
No Access
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VRAM cycle pattern (for VRAM-A1) bit: VRAM cycle pattern bit (VCP0A10 to VCP0A13,
VCP1A10 to VCP1A13, VCP2A10 to VCP2A13, VCP3A10 to VCP3A13, VCP4A10 to VCP4A13,
VCP5A10 to VCP5A13, VCP6A10 to VCP6A13, VCP7A10 to VCP7A13)
Sets the access command of the VRAM access that performs in VRAM-A1 timing T0
to T7.
When VRAM is not partitioned in two, the value of this register is ignored.
VRAM cycle pattern (for VRAM-B0) bit: VRAM cycle pattern bit (VCP0B00 to VCP0B03,
VCP1B00 to VCP1B03, VCP2B00 to VCP2B03, VCP3B00 to VCP3B03, VCP4B00 to VCP4B03,
VCP5B00 to VCP5B03, VCP6B00 to VCP6B03, VCP7B00 to VCP7B03)
Sets the access command of VRAM access that performs in VRAM-B0 (or VRAM-B)
timing T0 to T7.
VCP0A00~VCP0A03
180010H
Bit 12~15
VRAM-A0 (or VRAM-A) Timing for T0
VCP1A00~VCP1A03
180010H
Bit 8~11
VRAM-A0 (or VRAM-A) Timing for T1
VCP2A00~VCP2A03
180010H
Bit 4~7
VRAM-A0 (or VRAM-A) Timing for T2
VCP3A00~VCP3A03
180010H
Bit 0~3
VRAM-A0 (or VRAM-A) Timing for T3
VCP4A00~VCP4A03
180012H
Bit 12~15
VRAM-A0 (or VRAM-A) Timing for T4
VCP5A00~VCP5A03
180012H
Bit 8~11
VRAM-A0 (or VRAM-A) Timing for T5
VCP6A00~VCP6A03
180012H
Bit 4~7
VRAM-A0 (or VRAM-A) Timing for T6
VCP7A00~VCP7A03
180012H
Bit 0~3
VRAM-A0 (or VRAM-A) Timing for T7
VCP0A10~VCP0A13
180014H
Bit 12~15
VRAM-A1 Timing for T0
VCP1A10~VCP1A13
180014H
Bit 8~11
VRAM-A1 Timing for T1
VCP2A10~VCP2A13
180014H
Bit 4~7
VRAM-A1 Timing for T2
VCP3A10~VCP3A13
180014H
Bit 0~3
VRAM-A1 Timing for T3
VCP4A10~VCP4A13
180016H
Bit 12~15
VRAM-A1 Timing for T4
VCP5A10~VCP5A13
180016H
Bit 8~11
VRAM-A1 Timing for T5
VCP6A10~VCP6A13
180016H
Bit 4~7
VRAM-A1 Timing for T6
VCP7A10~VCP7A13
180016H
Bit 0~3
VRAM-A1 Timing for T7
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VCP0B00~VCP0B03
180018H
Bit 12~15
VRAM-B0 (or VRAM-B) Timing for T0
VCP1B00~VCP1B03
180018H
Bit 8~11
VRAM-B0 (or VRAM-B) Timing for T1
VCP2B00~VCP2B03
180018H
Bit 4~7
VRAM-B0 (or VRAM-B) Timing for T2
VCP3B00~VCP3B03
180018H
Bit 0~3
VRAM-B0 (or VRAM-B) Timing for T3
VCP4B00~VCP4B03
18001AH
Bit 12~15
VRAM-B0 (or VRAM-B) Timing for T4
VCP5B00~VCP5B03
18001AH
Bit 8~11
VRAM-B0 (or VRAM-B) Timing for T5
VCP6B00~VCP6B03
18001AH
Bit 4~7
VRAM-B0 (or VRAM-B) Timing for T6
VCP7B00~VCP7B03
18001AH
Bit 0~3
VRAM-B0 (or VRAM-B) Timing for T7
VRAM cycle pattern (for VRAM-B1) bit: VRAM cycle pattern bit (VCP0B10 to VCP0B13,
VCP1B10 to VCP1B13, VCP2B10 to VCP2B13, VCP3B10 to VCP3B13, VCP4B10 to VCP4B13,
VCP5B10 to VCP5B13, VCP6B10 to VCP6B13, VCP7B10 to VCP7B13).
Sets the access command of VRAM access that performs in VRAM-B1 timing T0 to
T7.
When VRAM is not partitioned into two areas, the value of this register is ignored.
VCP0B10~VCP0B13
18001CH
Bit 12~15
VRAM-B1 Timing for T0
VCP1B10~VCP1B13
18001CH
Bit 8~11
VRAM-B1 Timing for T1
VCP2B10~VCP2B13
18001CH
Bit 4~7
VRAM-B1 Timing for T2
VCP3B10~VCP3B13
18001CH
Bit 0~3
VRAM-B1 Timing for T3
VCP4B10~VCP4B13
18001EH
Bit 12~15
VRAM-B1 Timing for T4
VCP5B10~VCP5B13
18001EH
Bit 8~11
VRAM-B1 Timing for T5
VCP6B10~VCP6B13
18001EH
Bit 4~7
VRAM-B1 Timing for T6
VCP7B10~VCP7B13
18001EH
Bit 0~3
VRAM-B1 Timing for T7
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3.4 Color RAM Mode
With 32 Kbits (2 Kword) of color RAM, color data that is stored is used for all scroll
screens and palette format sprites. The color data selects and stores either RGB-5 bit
(15 bit data) or RGB-8 bit (24 bit data). In addition, when dividing it into 16K bits
(1K word) and storing various color data of the same type, the expansion color
calculation function can also be used. There are three methods for storing color data
in color RAM:
(1) Mode 0: RGB in each of 5 bits for a total of 15 bits, 1024 color settings
(2) Mode 1: RGB in each of 5 bits for a total of 15 bits, 2048 color settings
(3) Mode 2: RGB in each of 8 bits for a total of 24 bits, 1024 color settings
Because color data must be set to RGB-8 bit when it is output, a 0 will be added to
the lowest 3 bits if RGB-5 bit color data is stored in the color RAM, . When the
special color calculation mode is set to mode 3, the most significant bit of color RAM
data becomes the color calculation enable bit. See "12.3 Special Color Calculation
Function" about the special color calculation mode.
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Figure 3.9 shows the color data configuration of the color RAM.
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Dat a se t for RG B 8-b it
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Not e: The MSB CC is en abl e bi t wh en spe ci al co lo r cal cul ation mo de is mode 3.
Sha ded bit ar ea s are ign or ed .
CC
Dat a se t for RG B 5-b it
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
No te: The MSB CC is ena bl e bi t when spe cia l col or ca lcul at ion mode is mo de 3.
5 Bit Blue Dat a
5 Bit Green Da ta
5 Bit Red Data
Blue Data O ut put
Gree n Da ta Out put
Red Dat a Outpu t
Colo r Da ta
CC
0
0
0
0
0
0
0
0
0
5 Bit Blue Dat a
5 Bit G re en Dat a
5 Bit Re d Data
Co lor Dat a
Col or Data
8 Bit Blue Dat a
8 Bit Gre en Dat a
8 Bit Red Dat a
8 Bit Blue Dat a
8 Bit Gree n Dat a
8 Bit Red Dat a
Blue Dat a O ut put
Gree n Data Out put
Red Dat a Outpu t
Figure 3.9 Color data configuration on the color RAM
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Color data written to the color RAM is illustrated in Figure 3.10.
16 bit X 1024 Colors
2K Word
Same Color Data
Bit 0
100000H
100FFFH
Bit 1
100000H
100FFFH
Bit 2
100000H
100FFFH
16 bit X 1024 Colors
16 bit X 2048 Colors
32 bit X 1024 Colors
2K Word
1K Word
1K Word
Figure 3.10 Color Data of the Color RAM
RAM Control Register
The RAM control register selects the bank partitions of the VRAM, the purpose of
using the rotation scroll screen of VRAM, and the color RAM mode. It is a read/
write 16-bit register and is at the 18000EH address. Also, because the value is
cleared to 0, it must be set after the power is turned on or reset.
Color RAM Coefficient Table Enable Bit (CRKTE), Bit 15
See "6.4 Coefficient Table Control."
15
14
13
12
11
10
9
8
RAMCTL
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
18000EH
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00
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Color RAM mode bit (CRMD1, CRMD0), bits 13 and 12
Selects the color RAM mode. See "3.4 Color RAM mode."
Set the Color RAM mode to mode 1 when the CRKTE bit is 1. At that time, color
data can no longer be stored because the second half of the color RAM (100800H ~
100FFFH) is used for the coefficient table data.
Saving color data to the color RAM must be done after thes bits have been set.
When mode 0 is set, data written to the first half of the color RAM will be written to
the second half at the same time.
VRAM mode bit (VRBMD and VRAMD), bits 9 and 8. (See " 3.2 VRAM Bank Parti-
tion.")
Rotation data bank select bit: Data bank select bit (RDBSA01, RDBSA00, RDBSA11,
RDBSA10, RDBSB01, RDBSB00, RDBSB11, RDBSB10)
Designates the use objective of the VRAM of the rotation scroll screen. This bit is
only in effect when the rotation scroll screen is displayed. (See "6.2 Rotation Scroll
Screen Display Control.")
CRMD1
CRMD0
Mode
Process
0
0
0
RGB each 5 bits, 1024 color settings
0
1
1
RGB each 5 bits, 2048 color settings
1
0
2
RGB each 8 bits, 1024 color settings
1
1
-
Setting not allowed
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Chapter 4 Scroll Screen
4.1 Screen Display Control .............................................................................. 48
Screen Display Enable Register ........................................................... 48
4.2 Scroll Screen Structure .............................................................................. 50
Cell Format ........................................................................................... 50
Bit Map Format ..................................................................................... 52
4.3 Cell ............................................................................................................. 53
Character Color Number ...................................................................... 53
Cell Data Configuration ........................................................................ 53
Transparent Dots .................................................................................. 57
RGB Format Dot Data .......................................................................... 58
4.4 Character Patterns ..................................................................................... 59
Character Size and Cell Arrangement .................................................. 59
4.5 Character Control Register ........................................................................ 60
4.6 Pattern Name Table (Page) ........................................................................ 64
Pattern Name Table Data Configuration ............................................... 64
Pattern Name Data ............................................................................... 69
Character Number ................................................................................ 74
Palette Number ..................................................................................... 74
Special Function Bit .............................................................................. 74
Reverse (Flip) Function Bit ................................................................... 75
Pattern Name Control Register ............................................................ 76
4.7 Planes ........................................................................................................ 79
Plane Size ............................................................................................ 79
Plane Size Register .............................................................................. 80
4.8 Maps ........................................................................................................... 82
Map Selection Register ........................................................................ 82
Map Size ............................................................................................... 84
Map Offset Register .............................................................................. 85
Normal Scroll Screen Map Register ..................................................... 87
Rotation Scroll Surface Map Register .................................................. 89
4.9 Bit Maps ..................................................................................................... 93
Bit Map Size ......................................................................................... 93
Bit Map Color Number .......................................................................... 93
Bit Map Pattern ..................................................................................... 95
Bit Map Palatte Number ..................................................................... 111
Special Function Bit ............................................................................ 111
Bit Map Palatte Number Register ....................................................... 112
4.10 Display Area ........................................................................................... 114
Display Area ....................................................................................... 114
Screen-Over Process ......................................................................... 115
Display-Over Pattern Name ............................................................... 115
Screen-Over Pattern Name Register ................................................. 116
4.11 Mosaic Process ...................................................................................... 117
Mosaic Control Register ..................................................................... 118
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4.1 Screen Display Control
The scroll screen selects screens not displayed by controlling VRAM access used in
the display of each screen, and can also indicate whether to invalidate the dot color
code (transparency code) in each screen, which are the transparent dots of the screen
being displayed.
Screen Display Enable Register
The screen display enable register controls the screen display and transparency code.
With a write-only 16-bit register, its address is 180020H. Because the value of the
register is cleared to 0 after power on or reset, the value must be set.
Transparent display enable bit (N0TPON, N1TPON, N2TPON, N3TPON, R0TPON)
Designates whether to nullify the transparency code. For more specifics about the
transparency code see Transparent Dots in section "4.3 Cell."
Note: N0, N1, N2, N3, or R0 is entered into bit name for xx.
15
14
13
12
11
10
9
8
BGON
~
~
~
R0TPON
N3TPON
N2TPON
N1TPON
N0TPON
180020H
7
6
5
4
3
2
1
0
~
~
R1ON
R0ON
N3ON
N2ON
N1ON
N0ON
N0TPON
180020H
Bit 8
For NBG0 (or RBG1)
N1TPON
180020H
Bit 9
For NBG1 (or EXBG)
N2TPON
180020H
Bit 10
For NBG2
N3TPON
180020H
Bit 11
For NBG3
R0TPON
180020H
Bit 12
For RBG0
xxTPON
Process
0
Validates transparency code (transparency code dots become transparent)
1
Invalidates transparency code (transparency code dots are displayed according to da
values)
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Screen display enable bit: On bit (N0ON, N1ON, N2ON, N3ON, R0ON, R1ON)
Designates whether to display each scroll screen.
Note: N0, N1, N2, N3, R0, or R1 is entered into bit name xx.
When the screen access command (which has a 0 bit) is set in the VRAM cycle pat-
tern register, the access command is ignored and the VRAM access for displaying
the screen will not be performed.
When R0ON is 0, do not set R1ON at 1.
When both R0ON and R1ON are 1, the normal scroll screen can no longer be dis-
played. At this time, VRAM-B0 is fixed in RAM used for RBG1 character pattern
tables; and VRAM-B1 is fixed in RAM used for RBG1 pattern name tables.
When a specific screens can no longer be displayed by register settings, the screen bit
should be set to 0. For example, when both R0ON and R1ON are 1, set the N0ON,
N1ON, N2ON, N3ON bits at 0. See section "6.2 Rotation Scroll Surface Display
Control" for more about rotation scroll surfaces.
N0TPON
180020H
Bit 8
For NBG0 (or RBG1)
N1TPON
180020H
Bit 9
For NBG1 (or EXBG)
N2TPON
180020H
Bit 10
For NBG2
N3TPON
180020H
Bit 11
For NBG3
R0TPON
180020H
Bit 12
For RBG0
xxTPON
Process
0
Validates transparency code (transparency code dots become transparent)
1
Invalidates transparency code (transparency code dots are displayed according to da
values)
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4.2 Scroll Screen Structure
The scroll screen has two screen formats, the cell format and the bit map format.
Cell Format
The cell format scroll screen is composed of picture pattern "cells" that are 8 H dots
by 8 V dots; cells are arranged in 1 H X 1 V or 2 H X 2 V to form "character pat-
terns." A "page" is an arrangement of character patterns in 32 H X 32 V or 64 H X 64
V. A "plane" is an arrangement of pages 1 H X 1 V, 2 H X 1 V, or 2 H X 2 V. A
"map" is an arrangement of planes 2 H X 2 V (for normal scroll screens), or 4 H X 4
V (for rotation scroll surface). Figure 4.1 shows the cell format configuration of the
scroll screen.
8 H do t
X
8 V dot
Cell
Cha ra ct er
Pat ter n
1 H cel l
X
1 V cel l
or
2 H cel l
X
2 V cel l
Pag e
32 H X 32 V
or
64 H X 64 V
ch ar act er pa ttern
(64 H X 64 V ce ll )
Plane
1 H pa ge
X
1 V pa ge
or
2 H pa ge
X
1 V pa ge
or
2 H pa ge
X
2 V pa ge
Map
2 H pl an e
X
2 V pl an e
(n or mal scr ol l scr ee n)
or
4 H pl an e
X
4 V pl an e
(r ot at ion scr ol l scr ee n)
Figure 4.1 Scroll screen configuration of the cell format
Dot color data stored as character pattern tables in VRAM becomes cell data. Color
data is composed of 4, 8, 16, or 32-bit character color. Character pattern data is cell
data arranged in one or four pieces. Page data is character pattern name data (ad-
dress of character pattern table) stored as a pattern name table. Page data arranged
in one, two, or four pieces is a plane. The map selects the lead address of the pattern
name table in the map register and map offset register. Figure 4.2 shows the con-
figuration of a cell format of the scroll screen and corresponding data settings.
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C P0 Pa tt e rn N a me Da ta
Pa ttern Name Ta ble (V R AM)
Page 0
Page 1
Page 2
Page 3
N ote: Char acter patter n and pla ne siz e var y depen din g on the re g is ter setting; ma p siz e var ie s
d epending on the scro ll scre en type. T he above f ig u re is an exam ple of the ca se w hen cha ra cter
p atter n is 2 H cells X 2 V ce ll s. Th e plane is 2 H p ages X 2 V p ages and norm al sc r oll scre en
( 2 H planes X 2 V plane s) .
D ot 0 C olor D ata
C ell 0
C ell 1
C ell 2
C ell 3
Cha ra cter
Patte rn 0
C har act er Pat tern Ta ble ( VRAM )
Map
Map Register + Ma p Offse t Reg is ter
To p Addre ss of Pla n e A PN T
Plane A
PNT : Patte rn N ame Ta ble
CP : Char acter Patter n
Plane B
Plane C
Pla ne D
Ce ll
Dot 0
Do t 63
Do t 7
Dot 56
C har acter C ontr ol Register
Ch ara cter Co lo r Co unt
Pla ne
Page 1
Page 3
Pag e 0
Pag e 2
Pla n e Size
Plane Size R egist e r
C har act er Pa ttern
Cell 0
Cell 3
Cell 1
Cell 2
C har act er C ontr ol Register
C hara ct e r Size
CP10 23
Page
CP0
CP31
CP99 2
Patter n Na me D ata Size
Patte rn N ame C ontr ol Register
Plane A
To p A d dre ss of Plane B PNT
To p Addr ess o f Pla ne C PNT
To p Addre ss of Plane D PN T
C P1 02 3 P at ter n N am e D at a
C P0 Pat te rn N a me D a ta
C P1 02 3 Pa tt e rn N a me Da ta
C P1 0 23 Pa tt e rn N a me Da ta
C P0 Pat te rn N a me D a ta
CP 10 2 3 Pa tter n Na me D at a
CP 0 P at ter n N am e D at a
Dot 63 Co lo r Da ta
Dot 0 Color Dat a
Dot 63 Co lo r Da ta
Dot 0 Color Dat a
Dot 63 Co lo r Da ta
Dot 0 Color Dat a
Dot 63 Co lo r Da ta
Figure 4.2
Scroll screen configuration of cell format and corresponding data settings.
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Bit Map Format
The scroll screen of the bit map format is composed of a bit map pattern 512 H (or
1024) dots and 256 V (or 512) dots. When a screen is displayed by the bit map for-
mat, the size of the bit map must be set in the register and the set size of the bit map
pattern must be stored in VRAM. Figure 4.3 shows the scroll screen configuration of
the bit map format. Figure 4.4 shows the relationship of the register and the scroll
screen of the bit map format.
Bitmap
512 H X 256 V dot s
512 H X 512 V dot s
102 4 H X 25 6 Vdo ts
or
1024 H X 51 2 V do ts
1 Do t
Figure 4.3 Scroll screen configuration of the bit map format
Map Of fset Re gi st er
Map Off set
Bitmap Shap e
Cha ra ct er Cont rol Regi st er
Bitma p Size
Dot 0 Col or Data
VRAM
Cha ra ct er Con trol Reg ist er
Cha ra ct er Colo r Coun t
Bit ma p
Figure 4.4 Relationship of bit map format scroll screen and data settings
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4.3 Cell
The cell is a picture pattern 8 H dots by 8 V dots, and is stored in VRAM. The char-
acter color count (number of colors per one cell) can be selected from among 16, 256,
2048, 32,768, or 16,777,216 colors. The amount of RAM required in the size of each
dot color data and in data of one cell changes according to the color count.
Character Color Number
There are two color formats for displaying characters: the palette format and the
RGB format. The palette format treats display color data as color RAM address data
selected by the dot color code within cell data, and palette number within pattern
name data. The RGB format treats cell data as display color data. Table 4.1 shows
the character color count and the number of bits per dot at that time in the various
color formats.
Table 4.1 Character color count and dot data size
Note: In color RAM modes 0 and 2, 2048-color becomes 1024-color.
Cell Data Configuration
The data configuration of each cell stored in a character pattern table changes ac-
cording to the bit count of one dot. The boundary when stored in VRAM is 20H and
has no relationship to the bit count of one dot. Cell data configuration is shown in
Table 4.2 and Figure 4.5.
Table 4.2 Cell Data Configuration
Color Format
Character Color Count
Bit Count for 1 Dot
16 colors
4 bits
Palette Format
256 colors
8 bits
2048 colors
16 bits (Only use lower 11 bits)
RGB Format
32,768 colors
16 bits
16,770,000 colors
32 bits
(Only use MSB and lower 24 bits)
Bit Count for 1 Dot
Cell Data
Boundary
4 bits/dot
32 bytes/cell
20H byte
8 bits/dot
64 bytes/cell
20H byte
16 bits/dot
128 bytes/cell
20H byte
32 bits/dot
256 bytes/cell
20H byte
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Not e 1: The up pe r le ft not at ion in the cel l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num be rs in the cel ls ar e VRAM addr esses (Hexa de cim al ) of do t (2
do ts) da ta, wit h VRA M ad dr ess of dot 0- 0, 0- 1 dat a as the
ref ere nce .
Dot 0- 0 Dat a
bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00H
+02H
+1E H
Cha ra ct er Pat t er n Ta bl e (V RA M)
(1) 4 bi ts/ dot (32 byt es/ cel l)
Dot 0
1
2
3
4
5
6
7
Dot 0
1
2
3
4
5
6
7
Cel l
+00
+01
+02
+03
+04
+05
+06
+07
+08
+09
+0A
+0B
+ 0C
+ 0D
+0E
+0F
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+1A
+1B
+ 1C
+ 1D
+1E
+1F
Do t 0-4 Dat a
Dot 0- 1 Da ta
Dot 0-5 Dat a
Dot 0- 2 Da ta
Dot 0- 6 Da ta
Do t 7-4 Dat a
Dot 7- 5 Da ta
Do t 7-6 Dat a
Dot 0- 3 Da ta
Dot 7- 7 Da ta
Dot 0- 7 Da ta
Figure 4.5 Data configuration of cells by character color count
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+00
Dot 0
1
2
3
4
5
6
7
Dot 0
1
2
3
4
5
6
7
Not e 1: The uppe r lef t no tat ion in the ce ll is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num ber s in t he cel ls ar e VRAM ad dr esse s (Hexad eci mal ) of do t
da ta, with VRAM ad dr ess of dot 0- 0 dat a as the ref er en ce.
Cel l
Dot 0- 0 Dat a
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00H
+02H
+3E H
Cha ra ct er Pat t er n Ta bl e (V RA M)
(2) 8 bi ts/ dot (64 byt es/ cel l)
+01 +02 +03 +04 +05 +06 +07
+38 +39 +3A +3B + 3C + 3D +3E +3F
+08 +09 +0A +0B +0C +0D +0E +0F
+10 +11
+12 +13 +14 +15 +16 +17
+18 +19 +1A +1B +1C +1D +1E +1F
+20 +21 +22 +23 +24 +25 +26 +27
+28 +29 +2A +2B +2C +2D +2E +2F
+30 +31 +32 +33 +34 +35 +36 +37
Dot 0- 1 Dat a
Do t 0-3 Dat a
Dot 0- 2 Da ta
Dot 7- 6 Da ta
Dot 7- 7 Dat a
Figure 4.5 Data configuration of cells by character color count (continued)
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+00
Dot 0
1
2
3
4
5
6
7
Dot 0
1
2
3
4
5
6
7
Not e 1: The upp er lef t no tat io n in the ce ll is dot 0- 0; to the righ t ar e do t 0-1 ,
dot 0- 2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls are VRAM add re sses (Hexa de cim al) of dot
dat a, with VRAM ad dr ess of dot 0- 0 da ta as the re fer en ce.
Cel l
Dot 0- 1 Dat a
Dot 0- 0 Dat a
Dot 7- 7 Dat a
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00H
+02H
+7 EH
Cha ra ct er Pat t er n Ta bl e (V RA M)
(3) 16 bits/ do t (1 28 byt es/ ce ll )
+02 +04 +06 +08 +0A +0C +0E
+70 +72 +74 +76 +78 +7A +7C +7E
+10 +12 +14 +16 +18 +1A + 1C +1E
+20 +22 +24 +26 +28 +2A + 2C +2E
+30 +32 +34 +36 +38 +3A + 3C +3E
+40 +42 +44 +46 +48 +4A + 4C +4E
+50 +52 +54 +56 +58 +5A + 5C +5E
+60 +62 +64 +66 +68 +6A + 6C +6E
Figure 4.5 Data configuration of cells by character color count (continued)
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+00
Do t 0
1
2
3
4
5
6
7
Do t 0
1
2
3
4
5
6
7
Not e 1: The uppe r lef t no tat io n in the ce ll is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Numb er s in t he cel ls ar e VRAM addr esses (Hexadeci mal ) of do t
da ta (M SW), with VRAM ad dr ess of dot 0- 0 da ta (MSW) as the
ref ere nce .
Cel l
Dot 0- 0 Da ta (L ea st si gn ificant wor d)
Dot 0- 0 Da ta (M ost si gn if ica nt wor d)
Dot 7- 7 Da ta (L ea st si gn ificant wor d)
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00H
+02H
+F EH
Cha ra ct er Pat t er n Ta bl e (V RA M)
(4) 32 bits/ do t (2 56 byt es/ ce ll )
+04 +08 +0C +10 +14 +18 +1C
+E0 +E4 +E8 + EC +F 0 +F 4 +F8 +FC
Dot 0- 1 Da ta (M ost si gn if ica nt wor d)
Dot 7- 7 Da ta (M ost si gn if ica nt wor d)
+FCH
+0 4H
+20 +24 +28 + 2C +30 +34 +38 +3C
+40 +44 +48 + 4C +50 +54 +58 +5C
+60 +64 +68 + 6C +70 +74 +78 +7C
+80 +84 +88 + 8C +90 +94 +98 +9C
+A0 +A4 +A8 +AC +B0 +B4 +B8 +BC
+C0 + C4 + C8 +CC + D0 +D4 +D8 +D C
Transparent Dots
Dot color code, which are transparent dots (transparency code), changes according
to the color format. When the color format is the palette format, the transparent dot
applies when all bits per one dot is 0; when the RGB format, the transparent dot
applies when the most significant bit of the dot data is 0.
When in the palette format, lead color data of the palette corresponds to the trans-
parency code; therefore, it normally cannot be used. If the transparency code is
nullified, this color data can be used. Control is done by the screen display enable
register. Table 4.3 shows the transparent dot data values.
Figure 4.5 Data configuration of cells by character color count (continued)
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Table 4.3 Transparent dot data values
RGB Format Dot Data
When the color format is the RGB format, the character color count can be selected
from two groups: 32,768 colors and 16,770,000 colors. 16,770,000 colors are desig-
nated by RGB 8-bit; but 32,768 colors designate the higher 5 bits within RGB 8-bit,
and the lower 3 bits are set to 0. The transparency bit designates whether it is a
transparent dot. The most significant bit is a transparent dot when 0. In the screen
display enable register, when the transparency code is indicated as invalid, the
transparent bit is ignored. Figure 4.6 shows the dot data of the RGB format.
Bit 32
24
23
22
21
20
19
18
17
16
25
26
27
28
29
30
Tra nsp ar en t
Bit
Blue Da ta
3
2
1
0
4
5
6
Red Dat a
3
2
1
0
4
5
6
7
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Not e: Shade d bi ts are ign or ed
7
3
2
1
0
4
5
6
7
G re en Dat a
Wh en 16 ,770, 00 0 Col ors
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Blue Dat a
3
4
5
6
7
Wh en 32 76 8 Colo rs
3
4
5
6
7
3
4
5
6
7
Gree n Da ta
Re d Da ta
Tr an spa re nt
Bit
Figure 4.6 RGB format dot data
Color Format
Character Color
Count
Bit Count for 1 Dot
Transparency Code
16 colors
4 bits/dot
0H (4 bit)
Palette Format
256 colors
8 bits/dot
00H (8 bit)
2048 colors
16 bits/dot
000H (lower 11 bits)
RGB Format
32,768 colors
16 bits/dot
MSB (bit 15) is 0
16,770,000 colors
32 bits/dot
MSB (bit 31) is 0
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4.4 Character Patterns
Character patterns are perfect squares composed of 1 or 4 cells; the size is specified
in their respective registers.
Character Size and Cell Arrangement
When the character pattern is composed of four cells, the data of a cell that is used in
the same character pattern must be linked to and stored in a character pattern table.
The relationship of cell arrangement by character size (cell number of character
pattern) and character pattern table is shown in Figure 4.7.
8 dot
16 do t
16 do t
Cell Data 4
Cel l Dat a 3
Cel l Dat a 3
Cel l Dat a 2
Ce ll Da ta 0
Cel l Dat a 1
When 1 H cel l X 1 V cel l
When 2 H cel ls X 2 V cel ls
8 dot
Cell Data 0
Select ed
Cha ra ct er
Pattern
Addr ess
Hea de r
Addr ess
Cha ra ct er Pat t er n Ta bl e
Cel l Dat a 2
Ce ll Da ta 1
Ce ll Da ta 0
Figure 4.7 Cell Arrangement by Character Size
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4.5
Character Control Register
The character control register selects cell and bit map formats, the number of charac-
ter (bit map) colors, and the size of the character pattern or bit map. This register is
a write only 16-bit register located in addresses 180028H to 18002AH. Because the
value of the register is cleared to 0 after the power is turned on or reset, the value
must be set.
Character color number bit (N0CHCN2 to N0CHCN0, N1CHCN1, N1CHCN0, N2CHCN, N3CHCN,
R0CHCN2 to R0CHCN0)
Designates the character color count of each screen, and the bit map color count
when displaying by the bit map format.
Note:
Cannot be displayed by the exclusive monitor mode when used as RBG1.
15
14
13
12
11
10
9
8
CHCTLA
~
~
N1CHCN1 N1CHCN0 N1BMSZ1 N1BMSZ0 N1BMEN
N1CHSZ
180028H
7
6
5
4
3
2
1
0
~
N0CHCN2 N0CHCN1 N0CHCN0 N0BMSZ1 N0BMSZ0 N0BMEN
N0CHSZ
15
14
13
12
11
10
9
8
CHCTLB
~
R0CHCN2 R0CHCN1 R0CHCN0
~
R0BMSZ
R0BMEN
R0CHSZ
18002AH
7
6
5
4
3
2
1
0
~
~
N3CHCN
N3CHSZ
~
~
N2CHCN
N2CHSZ
N0CHCN2~N0CHCN0
180028H
Bit 6~4
For NBG0 (or RBG1)
N1CHCN1,N1CHCN0
180028H
Bit 13,12
For NBG1 (or EXBG)
N2CHCN
18002AH
Bit 1
For NBG2
N3CHCN
18002AH
Bit 5
For NBG3
R0CHCN2~R0CHCN0
18002AH
Bit 14~12
For RBG0
N0CHCN2
N0CHCN1
N0CHCN0
TV Screen Mode
Color
Normal
Hi-Res
Exclusive
Monitor
Format
0
0
0
16 colors
16 colors
16 colors
Palette Format
0
0
1
256 colors
256 colors
256 colors
Palette Format
0
1
0
2048 colors
2048 colors
2048 colors
Palette Format
0
1
1
32,786 colors
32,786 colors 32,786 colors
RGB Format
1
0
0
16,770,000
colors
Setting not
allowed
Setting not
allowed
RGB Format
1
0
1
Setting not allowed (Please do not set.)
1
1
0
Setting not allowed (Please do not set.)
1
1
1
Setting not allowed (Please do not set.)
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Note:
When used as EXBG, and when the set values are N1CHCN1 = 1, N1CHCN0 = 1 there are
16,770,000 colors
Note:
2 or 3 is entered in bit name for n.
Depending on the color count of NBG0 and NBG1, the scroll screen that cannot be
displayed will appear. When NBG0 is set at 2048 or 32,768 colors, NBG2 can no
longer be displayed. When NBG0 is set at 16,770,000 colors, NBG1 to NBG3 can no
longer be displayed. When NBG1 is set at 2048 or 32,768 colors, NBG3 can no longer
be displayed.
N1CHCN1
N1CHCN0
TV Screen Mode
Color Format
Normal
Hi-Res
Exclusive
Monitor
0
0
16 colors
16 colors
16 colors
Palette Format
0
1
256 colors
256 colors
256 colors
Palette Format
1
0
2048 colors
2048 colors
2048 colors
Palette Format
1
1
32,786 colors
32,786 colors
32,786 colors
RGB Format
NnCHCN0
TV Screen Mode
Color Format
Normal
Hi-Res
Exclusive
Monitor
0
16 colors
16 colors
16 colors
Palette Format
1
256 colors
256 colors
256 colors
Palette Format
R0CHCN2
R0CHCN1
R0CHCN0
TV Screen Mode
Color
Normal
Hi-Res
Exclusive
Monitor
Format
0
0
0
16 colors
16 colors
Cannot Display
Palette Format
0
0
1
256 colors
256 colors
Cannot Display
Palette Format
0
1
0
2048 colors
2048 colors
Cannot Display
Palette Format
0
1
1
32,786 colors
32,786 colors Cannot Display RGB Format
1
0
0
16,770,000
colors
Setting not
allowed
Cannot Display RGB Format
1
0
1
Setting not allowed (Please do not set.)
1
1
0
Setting not allowed (Please do not set.)
1
1
1
Setting not allowed (Please do not set.)
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Bit map size bit (N0BMSZ1, N0BMSZ0, N1BMSZ1, N1BMSZ0, R0BMSZ)
Designates the bit map size of each screen when display is in a bit map format.
Note: 0 or 1 is entered in bit name for n.
Bit map enable bit (N0BMEN, N1BMEN, R0BMEN)
Designates whether to display the scroll screen in a bit map format.
Note: N0, N1, or R0 is entered in bit name for xx.
N0BMSZ1,N0BMSZ0
180028H
Bit 3,2
For NBG0
N1BMSZ1,N1BMSZ0
180028H
Bit 11,10
For NBG1
R0BMSZ
18002AH
Bit 10
For RBG0
NnBMSZ1
NnBMSZ0
Bitmap Size
0
0
512 H dots X 256 V dots
0
1
512 H dots X 512 V dots
1
0
1024 H dots X 256 V dots
1
1
1024 H dots X 512 V dots
ROBMSZ
Bitmap Size
0
512 H dots X 256 V dots
1
512 H dots X 512 V dots
N0BMEN
180028H
Bit 1
For NBG0
N1BMEN
180028H
Bit 9
For NBG1
R0BMEN
18002AH
Bit 9
For RBG0
xxBMEN
Screen Display Format
0
Cell Format
1
Bitmap Format
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Character size bit (N0CHSZ, N1CHSZ, N2CHSZ, N3CHSZ, R0CHSZ)
Designates the character size when the scroll screen is in a cell format.
Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.
N0CHSZ
180028H
Bit 0
For NBG0 (or RBG1)
N1CHSZ
180028H
Bit 8
For NBG1
N2CHSZ
18002AH
Bit 0
For NBG2
N3CHSZ
18002AH
Bit 4
For NBG3
ROCHSZ
18002AH
Bit 8
For RBG0
x x C H S Z
Character Pattern Size
0
1 H Cell X 1 V Cell
1
2 H Cells X 2 V Cells
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4.6
Pattern Name Table (Page)
Pattern name table (or page) stores the method of arrangement when the character
pattern is in a square the size of a 64 X 64 cell in the VRAM. It also arranges pattern
name data in table form and stores it in VRAM. Pattern name data selects the lead
address of the character pattern stored in VRAM and the control information for
each character pattern. Pattern name data in a pattern name table is in one-word or
two-word. When in one-word, auxiliary data of the least significant 10 bits of the
pattern name control register is added to make up for insufficient bits.
Pattern Name Table Data Configuration
The boundary stored in VRAM and VRAM capacity required in a pattern name table
of 64 X 64 cells (1 page) change depending on the pattern name data size (word
count) and character size. The capacity and data configuration of pattern name
tables are shown in Table 4.4 and Figure 4.8.
Table 4.4 Pattern name table capacity and page boundary of one page
Pattern Name Data
Size
Character Size
Contents of 1
Page
Boundary During
VRAM Storage
1 Word
1 H Cell X 1 V Cell
8192 Bytes
2000H
2 H Cells X 2 V Cells
2048 Bytes
800H
2 Words
1 H Cell X 1 V Cell
16,384 Bytes
4000H
2 H Cells X 2 V Cells
4096 Bytes
1000H
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No te 1: The up per -lef t no tat ion in the page is ch ar act er pa ttern 0- 0; to the right ar e
char act er pat terns 0-1 , 0-2 , 0-3 , .. .
No te 2: Num be rs in the pag es are VRAM adr esse s (He xad eci mal ) of pa ttern na me dat a
of ch ar act er pa ttern s, with VRAM addr ess of cha ra ct er pat t er n 0-0 pat t er n nam e
dat a as the ref er en ce.
Cha ract er Pat ter n 0- 0 Pat t er n Name Dat a
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00 00H
+00 02H
+1F FEH
Pattern Nam e Ta bl e (V RA M)
(1) Pat tern Nam e Dat a Size : 1 wor d
Char act er Pat ter n Size : 1 H cel l X 1 V cel l
Ch ar act er
Pattern 0
1
2
63
Char act er
Pat ter n 0
1
62
63
Page
+000 0 +0002 +000 4
+0080 +0082 +0084
+1F0 0 +1F0 2 +1F0 4
+1F8 0 +1F8 2 +1F8 4
+007E
+007C
+007A
+00F E
+00FC
+00FA
+1F7 E
+1F7 C
+1F7 A
+1F FE
+1FFC
+1F FA
62
61
Char act er Patter n 0- 1 Pat ter n Na me Dat a
Char act er Pattern 63- 63 Patter n Nam e Data
addresses (Hexadecimal) of pattern name data
Figure 4.8 Data configuration of pattern name tables
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No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar e
cha ra ct er pat t er ns 0-1 , 0-2 , 0-3 , . ..
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as t he re fere nce .
Cha ract er Pat ter n 0- 0 Pat t er n Name Dat a
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+00 0H
+00 2H
+7FE H
Pattern Nam e Ta bl e (V RA M)
(2) Pat tern Nam e Dat a Size : 1 wor d
Char act er Pat ter n Size : 2 H cel ls X 2 V cel ls
Cha ract er
Pat ter n 0
1
2
Cha ra ct er
Pat t er n 0
1
30
31
Pag e
+000
+002
+004
+040
+042
+044
+780
+782
+784
+7C0
+7C2
+7C4
+03E
+03C
+03A
+07E
+07C
+07A
+7BE
+7BC
+7BA
+7FE
+7FC
+7FA
30
29
31
Cha ra ct er Pat t er n 31- 31 Pattern Nam e Da ta
Char act er Pattern 0-1 Pattern Nam e Da ta
addresses (Hexadecimal) of pattern name
Figure 4.8 Data configuration of pattern name tables (continued)
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No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar e
cha ra ct er pat t er ns 0-1 , 0-2 , 0-3 , . ..
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as t he re fere nce .
Pattern Nam e Ta bl e (V RA M)
(3) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 1 H cel l X 1 V cel l
Ch ar act er
Pattern 0
1
63
Cha ra ct er
Pat t er n 0
1
62
63
Pag e
+0000 +0004 +0008
+0100 +0104
+0108
+3E00 +3E04 +3E0 8
+3F0 0 + 3F 04 +3F0 8
+00FC
+00F8
+00F4
+01FC
+ 01 F 8
+ 01 F 4
+3EFC
+3EF8
+3EF 4
+3FF C
+3F F8
+3FF4
62
Ch ar act er Pattern 0- 0 Patter n Nam e Data (Most sig ni fica nt word )
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+000 0H
+000 2H
+3F FEH
+3F FCH
+000 4H
+0002 +0006 +000A
+0102 +0106
+010A
+3E02 +3E06 +3E0A
+3F0 2 + 3F 06 +3F0 A
+00FE
+00FA
+00F6
+01FE
+01FA
+ 01 F 6
+3EFE
+3EFA
+3EF 6
+3F FE
+3FFA
+3FF6
2
61
Cha ract er Pat ter n 0- 0 Pat t er n Name Dat a (Le ast si gni fican t word )
Char act er Pat ter n 0- 1 Pat t er n Name Dat a (Mo st si gni fican t wor d)
Char act er Patter n 63 -6 3 Pat t er n Name Dat a (Most si gni fican t wor d)
Char act er Pat ter n 63 -6 3 Pat t er n Name Dat a (Le ast sig ni fican t word )
addresses (Hexadecimal) of pattern name
Figure 4.8 Data configuration of pattern name tables (continued)
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No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar e
cha ra ct er pat t er ns 0-1 , 0-2 , 0-3 , . ..
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as t he re fere nce .
Pattern Nam e Ta bl e (V RA M)
(4) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 2 H cel ls X 2 V cel ls
Ch ar act er
Pattern 0
1
Char act er
Pat ter n 0
1
30
31
Pag e
+000
+004
+008
+080
+084
+088
+ F0 0
+ F0 4
+ F0 8
+F8 0
+ F8 4
+F8 8
+07C
+078
+074
+0F C
+0F8
+ 0F 4
+F 7C
+ F7 8
+F7 4
+F FC
+FF8
+F F4
29
31
Cha ra ct er Pat t er n 0-0 Pat tern Nam e Dat a (Mo st si gn ificant wor d)
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+0 00 H
+0 02 H
+FFEH
+FFCH
+0 04 H
+002
+006
+00A
+082
+086
+08A
+ F0 2
+ F0 6
+F0 A
+F8 2
+ F8 6
+F8 A
+07E
+07A
+076
+0FE
+0FA
+ 0F 6
+F7 E
+F7 A
+F7 6
+F FE
+F FA
+F F6
2
30
Char act er Patter n 0- 0 Pat ter n Na me Dat a (Le ast si gni fica nt wo rd )
Ch ar act er Pattern 0- 1 Pat ter n Na me Data (Most sig ni fica nt word )
Ch ar act er Pattern 31 -3 1 Pat ter n Na me Dat a (Most si gni fican t word )
Char act er Patter n 31 -3 1 Pat t er n Name Dat a (Le ast sig ni fica nt word )
addresses (Hexadecimal) of pattern name
Figure 4.8 Data configuration of pattern name tables (continued)
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Pattern Name Data
Pattern name data is composed of the following four fields, for a total of 26 bits.
Character number
15 bits
Palette number
7 bits
Special function bits
2 bits
Reverse function bits
2 bits
The character number designates the address of the character pattern (VRAM).
The palette number designates the address of the palette (color RAM) used by the
character. The special function bits designate whether that character will use the
special function. The reverse function bits designate whether to use the up-down
reverse or left-right reverse functions.
The size of the pattern name data in the pattern name table can select either 1-word
or 2-word. Because all required pattern name data cannot be designated when 1
word is selected, it is supplemented by auxiliary data of the least significant 10 bits
of the pattern name control register. The composition of pattern name data changes
depending on character size, character number color, and the character number
auxiliary mode. The character number auxiliary mode designates the number of bits
per character number when the pattern name table size in the pattern name table is
1-word, and whether that character can use the reverse function. Table 4.5 shows the
character number auxiliary mode. Figure 4.9 shows the configuration of 2-word
pattern name data, and Figure 4.10 shows the configuration of 1 word pattern name
data.
Table 4.5 Character number auxiliary mode
Bit 31
24
23
22
21
20
19
18
17
16
25
26
27
28
29
30
Palette Number
3
2
1
0
4
5
6
Character Number
PR
CC
10
11
12
13
14
PR: Special Priority Bit
CC: Special Color Calculation Bit
3
2
1
0
4
5
6
7
8
9
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Note: Shaded bits are ignored
Flip
Function
Special Function
Vertical
Horizontal
.
Figure 4.9 Bit configuration when the pattern name data is 2 word
Character Number
Auxiliary Mode
Process
0
Character number that can be specified in pattern name data is 10 bits.
Flip function can be specified in character units.
1
Character number that can be specified in pattern name data is 12 bits.
Flip function cannot be used.
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Table 4.6 shows the bit configuration when the pattern name data is 1 word.
Table 4.6 Bit configuration when pattern name data is 1 word
.
Note:
*1 Designates bits 9 to 0 in pattern name data.
*2 Designates bits 11 to 0 in pattern name data.
*3 Designates bits 11 to 2 in pattern name data.
*4 Designates bits 13 to 2 in pattern name data.
Character
Size
Character
Color Count
Auxiliary
Mode
Character
Number
Palette
Number
Special
Function
Flip Function
1 X 1
16
0
15
*
1
7
2
2
1 X 1
16
1
15
*
2
7
2
-
1 X 1
other than 16 0
15
*
1
3
2
2
1 X 1
other than 16 1
15
*
2
3
2
-
2 X 2
16
0
15
*
3
7
2
2
2 X 2
16
1
15
*
4
7
2
-
2 X 2
other than 16 0
15
*
3
3
2
2
2 X 2
other than 16 1
15
*
4
3
2
-
2 Words
15
7
2
2
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(1) Ch ar act er Size : 1 H cel l X 1 V cel l
Char act er Col or Coun t: 16 co lor s
Char act er Num be r Suppl eme nt Mo de : Mod e 0
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Palet te Num be r
Cha ra ct er Num ber
3
2
1
0
3
2
1
0
4
5
6
7
8
9
Pattern Nam e Data in Pattern Nam e Ta bl e
Bit 9
8
7
6
5
4
3
2
1
0
Spe ci al
Funct io n
Pale tte No.
Cha ra ct er Numb er
PR
CC
6
5
10
11
12
13
Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er
14
4
PR: Sp ecia l Pr io ri ty Bit
CC: Speci al Color Calc ula tion Bit
(2) Ch ar act er Size : 1 H cel l X 1 V cel l
Char act er Col or Coun t: 16 co lor s
Char act er Num be r Suppl eme nt Mo de : Mod e 1
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Palet te Num be r
Cha ra ct er Num ber
3
2
1
0
3
2
1
0
4
5
6
7
8
9
Pattern Nam e Data in Pattern Nam e Ta bl e
Bit 9
8
7
6
5
4
3
2
1
0
Pale tte No.
Ch ar act er Num be r
PR
CC
6
5
12
13
Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er
14
4
10
11
Not e: Sha de d bit s ar e ig no re d
Not e: Bot h ve rt ica l an d hor izont al flip fun ct ion bi ts are se t to 0.
(3) Ch ar act er Size : 1 H cel l X 1 V cel l
Char act er Col or Coun t:16
Char act er Num be r Suppl eme nt Mo de : Mod e 0
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Palet te Num be r
Cha ra ct er Num ber
6
5
4
3
2
1
0
4
5
6
7
8
9
Pattern Nam e Data in Pattern Nam e Ta bl e
Bit 9
8
7
6
5
4
3
2
1
0
Pal ette No .
Ch ar act er Num be r
PR
CC
12
13
14
10
11
Fli p Fun ct ion
Vert ica l
Hori zon tal
Speci al
Fun ct ion
PR: Speci al Pri ori ty Bit
CC: Sp ecia l Colo r Calcu latio n Bit
Not e: Sha de d bit is ign or ed
Fl ip Funct io n
Ver tical
Hor izon tal
Sup pl em ent al Da ta in Pat tern Nam e Cont ro l Regi st er
PR: Spec ial Prio r it y Bi t
C C: Speci al Color Calc ula tion Bi t
Speci al
Fun ct ion
Not e: Sha de d bits ar e ign or ed
Figure 4.10 Configuration when pattern name data is one word
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(4 ) Cha ra ct er Size : 1 H ce ll X 1 V ce ll
Cha ra ct er Colo r Coun t : Exce pt 16 col or s
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Pal et te Numb er
Cha ra ct er Numb er
6
5
4
3
2
1
0
4
5
6
7
8
9
Pattern Nam e Da ta in Pat tern Name Tab le
Bit 9
8
7
6
5
4
3
2
1
0
Pal et te No.
Cha ra ct er Num ber
PR
CC
12
13
14
10
11
(5 ) Cha ra ct er Size : 2 H ce ll s X 2 V ce ll s
Cha ra ct er Colo r Coun t : 16 Col or s
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Pal et te Numb er
Cha ra ct er Numb er
3
2
1
0
5
4
3
2
6
7
8
9
10
11
Pattern Nam e Da ta in Pat tern Name Tab le
Bit 9
8
7
6
5
4
3
2
1
0
Pal et te No.
Cha ra ct er Num ber
PR
CC
6
5
0
1
12
13
14
4
(6 ) Cha ra ct er Size : 2 H ce ll s X 2 V ce ll s
Cha ra ct er Colo r Coun t : 16 Col or s
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Pal et te Numb er
Char act er Nu mber
3
2
1
0
3
2
4
5
6
7
8
11
Pattern Nam e Da ta in Pat tern Name Tab le
Bit 9
8
7
6
5
4
3
2
1
0
Pal et te No.
Cha ra ct er Num ber
PR
CC
6
5
14
4
12
13
10
9
0
1
Speci al
Fun ct ion
Speci al
Fun ct ion
Spe cia l
Funct ion
PR : Speci al Pri orit y Bi t
CC: Sp ecia l C ol or Calcu lat ion Bi t
PR : Speci al Pri orit y Bi t
CC: Sp ecia l C ol or Calcu lat ion Bi t
Cha ra ct er Num ber Supp le me nt Mo de : Mod e 1
Not e: Bot h ver tica l and hor izo nt al flip fun ct ion bi ts are se t to 0.
Shad ed bi t is ig no re d
Suppl eme nt al Dat a in Pat t er n Na me Con trol Reg ist er
PR: Sp ecia l Pr io ri ty Bit
CC: Spec ial Colo r Calc ul atio n Bit
No te: Shad ed bi ts ar e igno re d
Cha ra ct er Num ber Supp le me nt Mo de : Mod e 0
Flip Fun ct ion
Vert ica l
Ho ri zo nt al
Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 1
Not e: Bot h ve rt ica l an d hor izon tal f li p fun ct ion bi ts ar e set t o 0.
Sup pl em ent al Da ta in Pat t er n Name Con tro l Reg ist er
No te: Shad ed bi ts ar e igno re d
Figure 4.10 Configuration when pattern name data is one word (continued)
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(7 ) Cha ra ct er Size : 2 H ce ll s X 2 V ce ll s
Cha ract er Co lor Cou nt : Exce pt 16 col or s
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Palet te Num be r
Cha ra ct er Nu mb er
6
5
4
3
2
4
5
6
7
8
9
Pattern Nam e Da ta in Pattern Nam e Tabl e
Bit 9
8
7
6
5
4
3
2
1
0
Pal et t e No.
Cha ra ct er Nu mb er
PR
CC
12
13
14
0
1
10
11
(8 ) Cha ra ct er Size : 2 H ce ll s X 2 V ce ll s
Cha ract er Co lor Cou nt : Exce pt 16 col or s
Bit 15
8
7
6
5
4
3
2
1
0
9
10
11
12
13
14
Palet t e Numb er
Cha ra ct er Nu mb er
6
5
4
3
2
4
5
6
7
8
9
Pattern Nam e Da ta in Pattern Nam e Tabl e
Bit 9
8
7
6
5
4
3
2
1
0
Pal et t e No.
Char act er Num be r
PR
CC
14
10
11
12
13
0
1
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 0
Suppl eme nt al Dat a in Pat ter n Na me Con trol Reg ist er
Note: Shad ed bi t is ig no re d
Flip Funct ion
Ver tical
Hor izo nt al
Speci al
Fun ct ion
PR: Sp ecia l Pr io ri ty Bit
CC: Spec ial Colo r Calc ula tio n Bit
Not e: Sha ded bit s ar e ig no re d
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 1
Not e: Bot h ve rt ica l an d hor izon tal f li p fun ct ion bi ts ar e se t t o 0.
Sha de d bit is ign or ed
Suppl eme nt al Dat a in Pat ter n Na me Con trol Reg ist er
Speci al
Fun ct ion
PR: Sp ecia l Pr io ri ty Bit
CC: Spec ial Colo r Calc ula tio n Bit
Not e: Shade d bi ts are ign or ed
Figure 4.10 Configuration when pattern name data is one word (continued)
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Character Number
The character number is 15-bit data, and designates the address of the character
pattern being displayed in that position. The boundary of the character pattern from
this character number is always 20H. Moreover, when the VRAM size is 4M bits, the
most significant bit of the character number (bit 14) is not used.
Palette Number
The palette number is 7-bit data, and designates the address of the color palette used
in the character pattern being displayed in that position. This data can be used only
when the color format is the palette format, not the RGB format. The palette number
is added to the dot color code of the character pattern. Because there is a total of 11
bits of dot color data, the bits that are used change depending on the character color
number. Figure 4.11 shows the configuration of 11-bit dot color data.
Pal ette Nu mbe r
3
2
1
0
4
5
6
3
2
1
0
Dot Col or Cod e
Cha ra ct er Colo r Co un t : 16 Col or s
Pal ette No .
7
6
5
4
4
5
6
3
2
1
0
Dot Col or Code
Cha ra ct er Colo r Coun t : 25 6 Colo rs
7
6
5
4
8
9
10
3
2
1
0
Do t Colo r Co de
Cha ra ct er Colo r Coun t : 20 48 Col or s
Figure 4.11 Dot color data by character color number
Special Function Bit
The special function bit is 2-bit data, and designates whether to use the special
function for the character pattern being displayed at that position. The special
function bit has a special priority bit that controls the priority number, and a special
color calculation bit that controls color operation. See "11.2 Special Priority Func-
tion" for more about the special priority bit, and "12.3 Special Color Calculation
Function" for more about the special color calculation bit.
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Reverse (Flip) Function Bit
The reverse function bit is 2-bit data, and designates whether to use the reverse
function for the character pattern being displayed at that position. The reverse
function bit has a top-bottom reverse bit that reverses the top and bottom of a char-
acter pattern, and a left-right reverse bit that reverses left and right. The reverse
function bit is shown in Table 4.7, and a reverse display of a character pattern in
shown in Figure 4.12.
Table 4.7 Reverse Function Bit
Figure 4.12 Reverse display of character patterns
Vertical Flip Bit
Horizontal Flip Bit
Process
0
0
Cannot flip vertically or horizontally
0
1
Horizontal flipping only
1
0
Vertical flipping only
1
1
Can flip both vertically and horizontally
Ver tical Flip Bit =0
Hor izon tal Flip Bit =0
Hori z. Flip
Ve rt. Flip
Hori z. and Ver t. Fli p
Ver tica l Fl ip Bit =1
Hor izon tal Flip Bit =0
Vert ica l Fli p Bit =1
Hori zon tal Fl ip Bit =1
Ver tical Flip Bit =0
Hor izo nt al Flip Bit =1
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Pattern Name Control Register
The pattern name control register assigns pattern name data size, character number
supplement mode, and pattern name supplement data. This register is a write only
16-bit register located in addresses 180030H to 180038H. Because the value of the
register is cleared to 0 after the power is turned on or reset, the value must be set.
Pattern name data size bit (N0PNB, N1PNB, N2PNB, N3PNB, R0PNB)
Designates the pattern name data size when displaying in the cell format.
15
14
13
12
11
10
9
8
PNCN0
N0PNB
N0CNSM
~
~
~
~
N0SPR
N0SCC
180030H
7
6
5
4
3
2
1
0
N0SPLT6 N0SPLT5 N0SPLT4
N0SCN4
N0SCN3
N0SCN2
N0SCN1
N0SCN0
15
14
13
12
11
10
9
8
PNCN1
N1PNB
N1CNSM
~
~
~
~
N1SPR
N1SCC
180032H
7
6
5
4
3
2
1
0
N1SPLT6 N1SPLT5 N1SPLT4
N1SCN4
N1SCN3
N1SCN2
N1SCN1
N1SCN0
15
14
13
12
11
10
9
8
PNCN2
N2PNB
N2CNSM
~
~
~
~
N2SPR
N2SCC
180034H
7
6
5
4
3
2
1
0
N2SPLT6 N2SPLT5 N2SPLT4
N2SCN4
N2SCN3
N2SCN2
N2SCN1
N2SCN0
15
14
13
12
11
10
9
8
PNCN3
N3PNB
N3CNSM
~
~
~
~
N3SPR
N3SCC
180036H
7
6
5
4
3
2
1
0
N3SPLT6 N3SPLT5 N3SPLT4
N3SCN4
N3SCN3
N3SCN2
N3SCN1
N3SCN0
15
14
13
12
11
10
9
8
PNCR
R0PNB
R0CNSM
~
~
~
~
R0SPR
R0SCC
180038H
7
6
5
4
3
2
1
0
R0SPLT6 R0SPLT5 R0SPLT4
R0SCN4
R0SCN3
R0SCN2
R0SCN1
R0SCN0
N0PNB
180030H
Bit 15
For NBG0 (or RBG 1)
N1PNB
180032H
Bit 15
For NBG1
N2PNB
180034H
Bit 15
For NBG2
N3PNB
180036H
Bit 15
For NBG3
R0PNB
180038H
Bit 15
For RBG0
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Note: N0, N1, N3, or R0 is entered in bit name for xx.
Character number supplement bit (N0CNSM, N1CNSM, N2CNSM, N3CNSM, R0CNSM)
Designates the character number supplement mode when the pattern name data size
in the pattern name table is 1-word.
Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.
Special priority bit (for pattern name supplement data): Supplementary special priority bit
(N0SPR, N1SPR, N2SPR, N3SPR, R0SPR)
Designates the pattern name supplement data as the special priority bit when the
pattern name data size is 1-word.
See "11.2 Special Color Priority Function" for how this bit is used.
N0CNSM
180030H
Bit 14
For NBG0 (or RBG 1)
N1CNSM
180032H
Bit 14
For NBG1
N2CNSM
180034H
Bit 14
For NBG2
N3CNSM
180036H
Bit 14
For NBG3
R0CNSM
180038H
Bit 14
For RBG0
x x C N S M
Character Number
Auxiliary Mode
Process
0
0
Character number in pattern name data is 10 bits.
Flip function can be selected in character units.
1
1
Character number in pattern name data is 12 bits.
Flip function cannot be used.
N0SPR
180030H
Bit 9
For NBG0 (or RBG 1)
N1SPR
180032H
Bit 9
For NBG1
N2SPR
180034H
Bit 9
For NBG2
N3SPR
180036H
Bit 9
For NBG3
R0SPR
180038H
Bit 9
For RBG0
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Pattern Name Data Size
0
2 Words
1
1 Word
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Special color calculation bit (for pattern name supplement data): Supplementary special color
calculation bit (N0SCC, N1SCC, N2SCC, N3SCC, R0SCC)
The special color calculation bit is designated as pattern name supplement data
when the pattern name data size is 1-word.
See "12.2 Special Color Calculation Function" to learn how this bit is used.
Supplementary palette number bit (N0SPLT6 to N0SPLT4, N1SPLT6 to N1SPLT4, N2SPLT6 to
N2SPLT4, N3SPLT6 to N3SPLT4, R0SPLT6 to R0SPLT4)
Designates the palette number bit as pattern name supplement data when the pat-
tern name data size is 1-word. Three bits are added to the palette number bit of the
pattern name data for the supplementary palette number bit.
Supplementary character number bit (N0SCN4 to N0SCN0, N1SCN4 to N1SCN0, N2SCN4 to
N2SCN0, N3SCN4 to N3SCN0, R0SCN4 to R0SCN0)
Designates the character number bit as the pattern name supplement data when the
pattern name data size is 1-word. Five bits are added to the palette number bit of
the pattern name data for the supplementary palette number bit.
N0SCC
180030H
Bit 8
For NBG0 (or RBG 1)
N1SCC
180032H
Bit 8
For NBG1
N2SCC
180034H
Bit 8
For NBG2
N3SCC
180036H
Bit 8
For NBG3
R0SCC
180038H
Bit 8
For RBG0
N0SPLT6~N0SPLT4
180030H
Bit 7~5
For NBG0 (or RBG 1)
N1SPLT6~N1SPLT4
180032H
Bit 7~5
For NBG1
N2SPLT6~N2SPLT4
180034H
Bit 7~5
For NBG2
N3SPLT6~N3SPLT4
180036H
Bit 7~5
For NBG3
R0SPLT6~R0SPLT4
180038H
Bit 7~5
For RBG0
N0SCN4~N0SCN0
180030H
Bit 4~0
For NBG0 (or RBG 1)
N1SCN4~N1SCN0
180032H
Bit 4~0
For NBG1
N2SCN4~N2SCN0
180034H
Bit 4~0
For NBG2
N3SCN4~N3SCN0
180036H
Bit 4~0
For NBG3
R0SCN4~R0SCN0
180038H
Bit 4~0
For RBG0
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4.7 Planes
Plane arranges the pattern name table (page) in sizes of 1 x 1, 2 x 1, or 2 x 2. Size is
designated in its respective register.
Plane Size
When the plane consists of more than one pattern name table (page), the pattern
name table used by one plane should be linked to VRAM and stored. Figure 4.13
shows the relationship of the pattern name table arranged by plane size (number of
plane page) and pattern name table.
Whe n 1 H page X 1 V pa ge
Pag e 0
Pag e 1
Pag e 2
Pag e 3
64 Cel ls
64 Cel ls
12 8 Cel ls
12 8 Cel ls
Pag e 0
Pag e 1
Pag e 2
Pag e 3
Select ed
Pattern Nam e
Tab le Heade r
Addr ess
Pat ter n Na me Tab le
Pag e 4
Pag e 1
64 Ce lls
12 8 Cel ls
Pag e 0
Whe n 2 H pa ge s X 1 V pa ge
Wh en 2 H pag es X 2 V page s
Page 0
Figure 4.13 Arrangement of pattern name table by plane size
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Plane Size Register
The plane size register controls the plane size and setting of the screen-over process
of the rotation scroll surface. This register is a write only 16-bit register located at
address 18003AH. Because the value of the register is cleared to 0 after the power is
turned on or reset, the value must be set.
Plane size bit (N0PLSZ1, N0PLSZ0, N1PLSZ1, N1PLSZ0, N2PLSZ1, N2PLSZ0, N3PLSZ1,
N3PLSZ0, RAPLSZ1, RAPLSZ0, RBPLSZ1, RBPLSZ0
)
Designates the plane size (number of pages) of each scroll screen.
Note: N0, N1, N2, N3, RA, or RB is entered in bit name for xx.
When the reduction display is set up to a factor of 1/4 in NBG0 and NBG1, do not
set the plane size of that screen to 2 H pages x 2 V pages.
15
14
13
12
11
10
9
8
PLSZ
RBOVR1
RBOVR0
RBPLSZ1 RBPLSZ0
RAOVR1
RAOVR0
RAPLSZ1 RAPLSZ0
18003AH
7
6
5
4
3
2
1
0
N3PLSZ1 N3PLSZ0 N2PLSZ1 N2PLSZ0 N1PLSZ1 N1PLSZ0 N0PLSZ1 N0PLSZ0
N0PLSZ1, N0PLSZ0
18003AH
Bit 1,0
For NBG0
N1PLSZ1, N1PLSZ0
18003AH
Bit 3,2
For NBG1
N2PLSZ1, N2PLSZ0
18003AH
Bit 5,4
For NBG2
N3PLSZ1, N3PLSZ0
18003AH
Bit 7,6
For NBG3
RAPLSZ1, RAPLSZ0
18003AH
Bit 9,8
For Rotation Parameter A
RBPLSZ1, RBPLSZ0
18003AH
Bit 13,12
For Rotation Parameter B
xxPLSZ1
xxPLSZ0
Plane Size
0
0
1 H Page X 1 V Page
0
1
2 H Pages X 1 V Page
1
0
Invalid (Do not set.)
1
1
2 H Pages X 2 V Pages
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Screen-over process bit: Over bit (RAOVR1, RAOVR0, RBOVR1, RBOVR0)
Designates control (screen-over process) when the display coordinate value exceeds
the display area in the rotation scroll surface.
Note: A or B is entered in bit name for x.
When the rotation scroll surface is in bit map, the character pattern designated by
the screen-over pattern name register must not be set to repeat process. With the
rotation scroll surface in bit map, and when the length of the bit map is 256 dots, if
the display area is set to 0
X < 512 and 0
Y < 512 and all the outer area is set to be
transparent, two of the same images will be displayed for each 256 V dots.
RAOVR1, RAOVR0
18003AH
Bit 11,10
For Rotation Parameter A
RBOVR1, RBOVR0
18003AH
Bit 15,14
For Rotation Parameter B
RxOVR1
RxOVR0
Screen Over Process
0
0
Outside the display area, the image set in the display area is repeated
0
1
Outside the display area, the character pattern specified by screen ove
pattern name register is repeated. (Only when the rotation scroll
surface is in cell format.)
1
0
Outside the display area, the scroll screen is transparent,
1
1
Set the display area as 0
X
512, 0
Y
512 regardless of plane size or
bitmap size and make that area transparent.
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4.8
Maps
Maps are square patterns consisting of 2 x 2 or 4 x 4 planes. A map of a Normal
scroll screen consists of a 2 x 2 plane, and a map of a rotation scroll surface consists
of a 4 x 4 plane. The method of arranging the plane is made by selecting the pattern
name table lead address in various plane registers.
Map Selection Register
Maps are organized into four planes (normal scroll screen) or 16 planes (rotation
scroll surface). Each screen has for each plane number a 6-bit map register to select
the pattern name table lead address for various planes. It also has a map offset
register of three bits added to the highest map register. The total 9-bit map selection
register changes the bit used and the register displaying the address value, depend-
ing on the pattern name data size and character size. Figure 4.14 shows the relation-
ship of the map register and map offset register.
Map Reg ist er A
3
2
1
0
4
5
Map Offse t Reg ist er
8
7
6
Ma p Re gi st er B
3
2
1
0
4
5
2
1
0
Ma p Re gi st er
3
4
5
6
7
8
Map Offse t Regi st er
Figure 4.14 Map selection register
Table 4.8 shows the address values of register and bits that are used for the map
selection register by the pattern name data size and character size.
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Table 4.8 Address value of map designated register by setting
Note: When the VRAM capacity is set at 4M bits, the most significant bit among the bits used is not
used.
Plane Size
Pattern Name
Data Size
Character Size
Bits and Addresses
1 Word
1 H Cell X 1 V Cell
(Value of bit 6~0) X 2000H
1 H page X
2 H Cells X 2 V Cells
(Value of bit 8~0) X 800H
1 V page
2 Words
1 H Cell X 1 V Cell
(Value of bit 5~0) X 4000H
2 H Cells X 2 V Cells
(Value of bit 7~0) X 1000H
1 Word
1 H Cell X 1 V Cell
(Value of bit 6~1) X 4000H
2 H pages X
2 H Cells X 2 V Cells
(Value of bit 8~1) X 1000H
1 V page
2 Words
1 H Cell X 1 V Cell
(Value of bit 5~1) X 8000H
2 H Cells X 2 V Cells
(Value of bit 7~1) X 2000H
1 Word
1 H Cell X 1 V Cell
(Value of bit 6~2) X 8000H
2 H pages X
2 V Cells X 2 V Cells
(Value of bit 8~2) X 2000H
2 V pages
2 Words
1 H Cell X 1 V Cell
(Value of bit 5~2) X 10000H
2 H Cells X 2 V Cells
(Value of bit 7~2) X 4000H
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Map Size
Map size (number of planes in the map) will change depending on if the screen is a
normal scroll screen or rotation scroll surface. The normal scroll screen has a map 2
H planes X 2 V planes in each screen. The rotation scroll surface has a map 4 H
planes X 4 V planes in both of rotation parameters A and B. Figure 4.15 shows the
plane arrangements of different map sizes.
Plane
A
Normal Scroll Screen
Rotation Scroll Screen
Plane
B
Plane
C
Plane
D
Plane
A
Plane
B
Plane
E
Plane
F
Plane
C
Plane
D
Plane
G
Plane
H
Plane
I
Plane
J
Plane
M
Plane
N
Plane
K
Plane
L
Plane
O
Plane
P
Figure 4.15 Map size
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When NBG0 and NBG1 enable bits (N0ZMQT and N1ZMQT) are set to allow reduc-
tion up to a factor of 1/4, the map size of NBG0 and NBG1 become normal. A set
screen plane size, that can be reduced up to 1/4 should not be 2 H pages X 2 V
pages. Figure 4.16 shows the map size by the reduction setting.
When se tting NBG0, ca n
be red uce d up t o 1/4.
Plan e A
For NB G0
Plan e B
Fo r NBG0
Pla ne D
For NBG 0
Plane C
For NBG0
Plan e A
For NB G2
Plan e B
Fo r NBG2
Pla ne D
For NBG 2
Plane C
For NBG2
Plane A
For NBG1
Plane B
For NBG1
Plane D
For NBG1
Plan e C
For NB G1
Plane A
For NBG3
Plane B
For NBG3
Plane D
For NBG3
Plan e C
For NB G3
Whe n se tting NBG1, ca n
be red uce d up t o 1/4.
Figure 4.16 Plane arrangement of map by reduction settings
Map Offset Register
The map offset register designates the map offset value. This is a write-only 16-bit
register, with addresses located at 18003CH to 18003EH. Because the value of the
register is cleared to 0 after the power is turned on or reset, the value must be set.
15
14
13
12
11
10
9
8
MPOFN
~
N3MP8
N3MP7
N3MP6
~
N2MP8
N2MP7
N2MP6
18003CH
7
6
5
4
3
2
1
0
~
N1MP8
N1MP7
N1MP6
~
N0MP8
N0MP7
N0MP6
15
14
13
12
11
10
9
8
MPOFR
~
~
~
~
~
~
~
~
18003EH
7
6
5
4
3
2
1
0
~
RBMP8
RBMP7
RBMP6
~
RAMP8
RAMP7
RAMP6
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Map offset bit (N0MP8 to N0MP6, N1MP8 to N1MP6, N2MP8 to N2MP6, N3MP8 to N3MP6,
RAMP8 to RAMP6, RBMP8 to RBMP6)
When the scroll screen display format is the cell format, the map offset value of 3 bits
is added to the highest 6 bits of the map register. This designates the bit map pattern
boundary when in the bit map format.
Boundary address of the bit map pattern is shown below:
(boundary address value of the bit map pattern) = (map offset register value 3 bit) x
20000H.
N0MP8~N0MP6
18003CH
Bit 2~0
For NBG0
N1MP8~N1MP6
18003CH
Bit 6~4
For NBG1
N2MP8~N2MP6
18003CH
Bit 10~8
For NBG2
N3MP8~N3MP6
18003CH
Bit 14~12
For NBG3
RAMP8~RAMP6
18003EH
Bit 2~0
For Rotation Parameter A
RBMP8~RBMP6
18003EH
Bit 6~4
For Rotation Parameter B
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Normal Scroll Screen Map Register
Normal scroll screen map register designates the lead address of the pattern name
table of each plane when the normal scroll screen is displayed in the cell format.
This register is a write-only 16-bit register, with addresses located at 180040H to
18004EH. Because the value of the register is cleared to 0 after the power is turned
on or reset, the value must be set.
15
14
13
12
11
10
9
8
MPABN0
~
~
N0MPB5
N0MPB4
N0MPB3
N0MPB2
N0MPB1
N0MPB0
180040H
7
6
5
4
3
2
1
0
~
~
N0MPA5
N0MPA4
N0MPA3
N0MPA2
N0MPA1
N0MPA0
15
14
13
12
11
10
9
8
MPCDN0
~
~
N0MPD5
N0MPD4
N0MPD3
N0MPD2
N0MPD1
N0MPD0
180042H
7
6
5
4
3
2
1
0
~
~
N0MPC5
N0MPC4
N0MPC3
N0MPC2
N0MPC1
N0MPC0
15
14
13
12
11
10
9
8
MPABN1
~
~
N1MPB5
N1MPB4
N1MPB3
N1MPB2
N1MPB1
N1MPB0
180044H
7
6
5
4
3
2
1
0
~
~
N1MPA5
N1MPA4
N1MPA3
N1MPA2
N1MPA1
N1MPA0
15
14
13
12
11
10
9
8
MPCDN1
~
~
N1MPD5
N1MPD4
N1MPD3
N1MPD2
N1MPD1
N1MPD0
180046H
7
6
5
4
3
2
1
0
~
~
N1MPC5
N1MPC4
N1MPC3
N1MPC2
N1MPC1
N1MPC0
15
14
13
12
11
10
9
8
MPABN2
~
~
N2MPB5
N2MPB4
N2MPB3
N2MPB2
N2MPB1
N2MPB0
180048H
7
6
5
4
3
2
1
0
~
~
N2MPA5
N2MPA4
N2MPA3
N2MPA2
N2MPA1
N2MPA0
15
14
13
12
11
10
9
8
MPCDN2
~
~
N2MPD5
N2MPD4
N2MPD3
N2MPD2
N2MPD1
N2MPD0
18004AH
7
6
5
4
3
2
1
0
~
~
N2MPC5
N2MPC4
N2MPC3
N2MPC2
N2MPC1
N2MPC0
15
14
13
12
11
10
9
8
MPABN3
~
~
N3MPB5
N3MPB4
N3MPB3
N3MPB2
N3MPB1
N3MPB0
18004CH
7
6
5
4
3
2
1
0
~
~
N3MPA5
N3MPA4
N3MPA3
N3MPA2
N3MPA1
N3MPA0
15
14
13
12
11
10
9
8
MPCDN3
~
~
N3MPD5
N3MPD4
N3MPD3
N3MPD2
N3MPD1
N3MPD0
18004EH
7
6
5
4
3
2
1
0
~
~
N3MPC5
N3MPC4
N3MPC3
N3MPC2
N3MPC1
N3MPC0
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Map bit (for normal scroll): (N0MPA5 to N0MPA0, N0MPB5 to N0MPB0,
N0MPC5 to N0MPC0, N0MPD5 to N0MPD0, N1MPA5 to N1MPA0, N1MPB5 to N1MPB0, N1MPC5
to N1MPC0, N1MPD5 to N1MPD0, N2MPA5 to N2MPA0, N2MPB5 to N2MPB0, N2MPC5 to
N2MPC0, N2MPD5 to N2MPD0, N3MPA5 to N3MPA0, N3MPB5 to N3MPB0, N3MPC5 to N3MPC0,
N3MPD5 to N3MPD0)
The lead address for the pattern name table is designated for each plane, when the
Normal scroll screen is displayed by the cell format.
N0MPA5~N0MPA0
180040H
Bit 5~0
For NBG0 Plane A
N0MPB5~N0MPB0
180040H
Bit 13~8
For NBG0 Plane B
N0MPC5~N0MPC0
180042H
Bit 5~0
For NBG0 Plane C
N0MPD5~N0MPD0
180042H
Bit 13~8
For NBG0 Plane D
N1MPA5~N1MPA0
180044H
Bit 5~0
For NBG1 Plane A
N1MPB5~N1MPB0
180044H
Bit 13~8
For NBG1 Plane B
N1MPC5~N1MPC0
180046H
Bit 5~0
For NBG1 Plane C
N1MPD5~N1MPD0
180046H
Bit 13~8
For NBG1 Plane D
N2MPA5~N2MPA0
180048H
Bit 5~0
For NBG2 Plane A
N2MPB5~N2MPB0
180048H
Bit 13~8
For NBG2 Plane B
N2MPC5~N2MPC0
18004AH
Bit 5~0
For NBG2 Plane C
N2MPD5~N2MPD0
18004AH
Bit 13~8
For NBG2 Plane D
N3MPA5~N3MPA0
18004CH
Bit 5~0
For NBG3 Plane A
N3MPB5~N3MPB0
18004CH
Bit 13~8
For NBG3 Plane B
N3MPC5~N3MPC0
18004EH
Bit 5~0
For NBG3 Plane C
N3MPD5~N3MPD0
18004EH
Bit 13~8
For NBG3 Plane D
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Rotation Scroll Surface Map Register
The Rotation Scroll Surface Map Register designates the lead address of the pattern
name table arranged in each plane by rotation parameters A and B. When a write-
only 16-bit register, with addresses located at 180050H to 18006EH. Because the
value of the register is cleared to 0 after the power is turned on or reset, the value
must be set.
15
14
13
12
11
10
9
8
MPABRA
~
~
RAMPB5
RAMPB4
RAMPB3
RAMPB2
RAMPB1
RAMPB0
180050H
7
6
5
4
3
2
1
0
~
~
RAMPA5
RAMPA4
RAMPA3
RAMPA2
RAMPA1
RAMPA0
15
14
13
12
11
10
9
8
MPCDRA
~
~
RAMPD5
RAMPD4
RAMPD3
RAMPD2
RAMPD1
RAMPD0
180052H
7
6
5
4
3
2
1
0
~
~
RAMPC5
RAMPC4
RAMPC3
RAMPC2
RAMPC1
RAMPC0
15
14
13
12
11
10
9
8
MPEFRA
~
~
RAMPF5
RAMPF4
RAMPF3
RAMPF2
RAMPF1
RAMPF0
180054H
7
6
5
4
3
2
1
0
~
~
RAMPE5
RAMPE4
RAMPE3
RAMPE2
RAMPE1
RAMPE0
15
14
13
12
11
10
9
8
MPGHRA
~
~
RAMPH5
RAMPH4
RAMPH3
RAMPH2
RAMPH1
RAMPH0
180056H
7
6
5
4
3
2
1
0
~
~
RAMPG5
RAMPG4
RAMPG3
RAMPG2
RAMPG1
RAMPG0
15
14
13
12
11
10
9
8
MPIJRA
~
~
RAMPJ5
RAMPJ4
RAMPJ3
RAMPJ2
RAMPJ1
RAMPJ0
180058H
7
6
5
4
3
2
1
0
~
~
RAMPI5
RAMPI4
RAMPI3
RAMPI2
RAMPI1
RAMPI0
15
14
13
12
11
10
9
8
MPKLRA
~
~
RAMPL5
RAMPL4
RAMPL3
RAMPL2
RAMPL1
RAMPL0
18005AH
7
6
5
4
3
2
1
0
~
~
RAMPK5
RAMPK4
RAMPK3
RAMPK2
RAMPK1
RAMPK0
15
14
13
12
11
10
9
8
MPMNRA
~
~
RAMPN5
RAMPN4
RAMPN3
RAMPN2
RAMPN1
RAMPN0
18005CH
7
6
5
4
3
2
1
0
~
~
RAMPM5 RAMPM4 RAMPM3 RAMPM2 RAMPM1 RAMPM0
15
14
13
12
11
10
9
8
MPOPRA
~
~
RAMPP5
RAMPP4
RAMPP3
RAMPP2
RAMPP1
RAMPP0
18005EH
7
6
5
4
3
2
1
0
~
~
RAMPO5
RAMPO4
RAMPO3
RAMPO2
RAMPO1
RAMPO0
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15
14
13
12
11
10
9
8
MPABRB
~
~
RBMPB5
RBMPB4
RBMPB3
RBMPB2
RBMPB1
RBMPB0
180060H
7
6
5
4
3
2
1
0
~
~
RBMPA5
RBMPA4
RBMPA3
RBMPA2
RBMPA1
RBMPA0
15
14
13
12
11
10
9
8
MPCDRB
~
~
RBMPD5
RBMPD4
RBMPD3
RBMPD2
RBMPD1
RBMPD0
180062H
7
6
5
4
3
2